Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2001-03-09
2002-07-23
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S118000
Reexamination Certificate
active
06424282
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to noise compensation methods and apparatuses and, in particular, to methods and apparatuses for performing noise cancellation in digital-to-analog converter applications.
With reference to
FIG. 1
, a conventional digital-to-analog converter (DAC)
10
produces an analog output signal (analog data) in response to a digital input signal (digital data). For example, the digital input signal may be a series of digital words containing a certain number of bits and the DAC
10
produces an analog output signal having a series of amplitudes corresponding to the digital words. The DAC
10
receives a clock signal CLK (also referred to as a word clock signal) and a voltage reference signal (Vref). The Vref signal is usually a DC level, such as 5 volts, 10 volts, etc.
The DAC
10
utilizes the DC level of the Vref signal in producing a given amplitude of the analog output signal in response to a particular digital word. Mathematically, the digital words may be thought of as fractions of unity (or percentages) that multiply the DC value of the Vref signal to produce the corresponding amplitudes of the analog output signal. For example, assuming that the digital input signal is composed of three bit digital words, the digital word 000 may represent a minimum digital magnitude and the digital word 111 may represent a digital maximum magnitude. The DAC
10
treats each digital word as a multiplier that modifies the Vref signal to produce the analog output signal. Thus, for example, the digital word 000 may be treated as a multiplier having a value of 0, the digital word 001 may be treated as a multiplier having a value of 0.125, the digital word
010
may be treated as a multiplier having a value of 0.250, etc. Thus, assuming that the Vref signal is 10 volts, the amplitude of the analog output signal in response to the digital word 010 in this example would be 0.250×10=2.5 volts.
The word clock signal CLK is utilized by the DAC
10
to establish the particular instances in time that the amplitude of the analog output signal should change in response to new digital words. Conventional DACs produce new amplitudes of the analog output signal on one of the rising and falling edges of the word clock signal CLK.
With reference to
FIGS. 2A and 2B
, the conventional DAC
10
exhibits undesirable performance when noise appears on the word clock signal CLK.
FIG. 2A
illustrates the ideal falling edges of the word clock signal CLK, which for the purposes of this discussion are utilized by the DAC
10
to indicate when the amplitude of the analog output signal should be transitioned. The ideal falling edges of the word clock signal CLK occur at t
1
, t
2
, t
3
, etc. In a practical circuit, however, the falling edges of the word clock signal CLK may occur at different instances due to noise. As the noise on the word clock signal CLK affects the timing of the falling edges, it is referred to herein as timing noise, but is also referred to in the art as jitter. By way of example, jitter on the word clock signal CLK may cause falling edges to occur at t
1
−&Dgr;t, t
2
−&Dgr;t, etc. As will be discussed hereinbelow, the jitter may be time invariant (e.g., producing a fixed &Dgr;t) or may be time variant (e.g., producing a &Dgr;t that changes with time).
Reference is now made to
FIG. 2B
which illustrates an affect that jitter on the word clock signal CLK may have on the analog output signal from the DAC
10
. The solid line of
FIG. 2B
is intended to illustrate an ideal analog output signal from the DAC
10
in response to different digital words of the digital input signal. For simplicity, the ideal analog output signal is illustrated as a series of piecewise linear segments, although it is understood that a practical DAC produces a stepped response. Conceptually, the piecewise linear segments shown in
FIG. 2B
may be thought of as time integrals of the stepped output from the DAC
10
as may be produced by a filter.
Transitions in the analog output signal ideally occur at times t
1
, t
2
, t
3
, etc. Continuing with the example above and assuming that the digital word input to the DAC
10
was 011 just prior to time t
1
, the ideal analog output signal would be 3.75 volts at t
1
. Assuming that the digital word input to the DAC
10
just prior to time t
2
was 111, the analog output signal would ideally be 10 volts at time t
2
. Similarly, if the digital word input to be DAC
10
just prior to time t
3
was 011, then the analog output signal would ideally be 3.75 volts at time t
3
.
Assuming some jitter on the word clock signal CLK, however, the transitions of the analog output signal from the DAC
10
might not occur at the ideal times of t
1
, t
2
, t
3
, etc. Indeed, assuming a time invariant jitter of &Dgr;t, the transitions of the analog output signal would occur at the wrong times, e.g., t
1
−&Dgr;t, t
2
−&Dgr;t, t
3
−&Dgr;t, etc. In keeping with the above example, the amplitude of the analog output signal would be: (i) 3.75 volts at t
1
−&Dgr;t, (ii) 10.00 volts at time t
2
−&Dgr;t, and (iii) 3.75 volts at time t
3
−&Dgr;t. The piecewise linear approximation of the analog output signal as affected by jitter is shown in
FIG. 2B
by way of dashed line and labeled non-ideal analog output signal (jitter). Comparisons of the ideal analog output signal and the non-ideal analog signal due to jitter on the word clock signal CLK reveal that producing the right amplitudes at the wrong times is the same as producing the wrong amplitudes at the ideal times of t
1
, t
2
, t
3
, etc. Consequently, jitter on the word clock signal CLK produces errors in the amplitude of the analog output signal.
With reference to
FIG. 2C
, the Vref signal may include amplitude noise. By way of example, the amplitude noise illustrated in
FIG. 2C
is time invariant after time t
1
, although it is understood that the amplitude noise on the Vref signal may also be time variant (as will be discussed hereinbelow). Referring again to
FIG. 2B
, amplitude noise on the Vref signal will produce errors in the analog output signal from the DAC
10
. In keeping with the digital words of 011, 111, and 011 in the above example, time invariant amplitude noise on the Vref signal (assuming no jitter on the word clock signal CLK) would produce an analog output signal from the DAC
10
having amplitudes at the ideal times of t
1
, t
2
, t
3
, etc. that are offset from the ideal amplitudes of 3.75 volts, 10.00 volts, 3.75 volts, respectively. In particular, the amplitude noise on the Vref signal illustrated in
FIG. 2C
, may be of sufficient magnitude to cause the amplitudes of the analog output signal of the DAC
10
to be 5.00 volts, 11.25 volts, and 5.00 volts at respective times t
1
, t
2
, t
3
, etc. These non-ideal amplitudes of the analog output signal are shown in
FIG. 2B
in dashed line and labeled non-ideal analog output signal (amp. noise). A comparison of the ideal analog output signal to the non-ideal output signal due to amplitude noise on the Vref signal reveals that the amplitude noise on the Vref signal produces amplitude errors in the analog output signal.
As discussed above, the jitter on the word clock signal CLK and/or the amplitude noise on the Vref signal may be time variant. Indeed, the jitter and/or the amplitude noise may contain energy at a single frequency (e.g., pure sinusoidal noise) or may contain energy at a number of discreet frequencies or even many discreet frequencies (e.g., white noise).
With reference to
FIGS. 3A-3F
, illustrative examples of the affects that time variant amplitude noise on the Vref signal and time variant jitter on the word clock signal CLK have on the analog output signal of the DAC
10
will now be discussed. With reference to
FIG. 3A
, an ideal analog output signal from the DAC
10
in response to a digital input signal consistent with a pure sine wave having a frequency of about 20 KHz is illustrated. The ideal analog output signal shown in
FIG. 3A
would be p
Jeanpierre Peguy
Lauture Joseph J
Lerner David Littenberg Krumholz & Mentlik LLP
Sony Corporation
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