Patent
1997-04-30
1999-07-27
Lee, Thomas C.
395826, 395828, 395855, 395877, G06F 1300
Patent
active
059305258
ABSTRACT:
Disclosed are methods and apparatuses for use with a host computer system that optimize the timing and sizing of data blocks that are part of an ATM PDU that is to be transmitted over an ATM network. The data blocks are transferred from the host's memory to a local memory in a network interface circuit. The network interface circuit includes a memory access circuit, a segmenting circuit, a local memory, and a scheduling circuit. The memory access circuit accesses the host's memory and fetches an initial size block of a data packet therefrom and supplies the block of the data to the segmenting circuit which segments the block of the data into a plurality of linked cells. The plurality of linked cells are then stored in the local memory. The scheduling circuit retrieves the linked cells in a predetermined order and transmits each of them over a network connection at a specific time. When the remaining number of the stored plurality of linked cells falls below a defined level, the scheduling circuit requests that the memory access circuit fetch subsequent or burst size block of the data packet. This process continues until such time as all of the data packet has been transmitted over the network connection.
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Chai Jen Ming
Gotesman Joel
Adaptec, Inc.
Lee Thomas C.
Smith Michael G.
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