Method and apparatus for multiplying two numbers using signed ar

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3647365, 364737, G06F 752, G06F 700, G06F 1100

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054228050

ABSTRACT:
A signed arithmetic data processing system (20) detects a multiply (MUL) or a multiply-and-accumulate (MAC) instruction in which a multiplier and a multiplicand each assume their respective maximum negative values. If one or both of the operands is not equal to its maximum negative value, the multiplication proceeds normally, such as in a modified Booth's multiplier/MAC (33). However, if both operands are equal to their respective maximum negative values, the data processing system (20) substitutes a maximum positive constant for the output of the multiplier/MAC (33). This substitution allows the result to be expressed with one fewer bits. The resulting error is very small and becomes insignificant in most digital signal processing algorithms, especially those based on fractional, saturation arithmetic. Alternatively, an extra bit of precision may be achieved for a given hardware size.

REFERENCES:
patent: 4649508 (1987-03-01), Kanuma
patent: 4789956 (1988-12-01), Hildebrandt
patent: 4941119 (1990-07-01), Moline
patent: 4945507 (1990-07-01), Ishida et al.
patent: 5038313 (1991-08-01), Kojima
patent: 5128890 (1992-07-01), Girardeau
patent: 5262973 (1993-11-01), Richardson

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