Boots – shoes – and leggings
Patent
1993-02-01
1994-09-13
Mai, Tan V.
Boots, shoes, and leggings
364757, G06F 738, G06F 752
Patent
active
053474813
ABSTRACT:
A structure of logic gates, partial product circuits, and a multiplier tree is described for multiplying of two operands which may contain denormalized numbers in the same amount of time as needed to multiply normalized numbers. The generation of the most significant bits ("hidden bits") of the significands of the operands from the operand exponents, and the production of the partial products that are dependent on these hidden bits, is accomplished in parallel with the generation of the partial products of the expressed bits of the significands of the operands and the first level of the multiplier tree. The fraction field partial products are input into the top level of a multiplier tree comprised of various order adders and wires. The hidden bit partial products are then input into the body of the multiplier tree instead of the top level. Additional adders are allocated to accommodate these additional inputs, but without lengthening the longest serial path from the top to the bottom of the multiplier tree. The result of the multiplier tree is summed and output. The parallel processing arrangement allows the identification and multiplication of denormalized numbers without any added delay due to the generation of the hidden bits.
REFERENCES:
patent: 4338675 (1982-07-01), Palmer et al.
patent: 5195051 (1993-03-01), Palaniswami
Wallace, C. S., "A Suggestion for a Fast Multiplier", IEEE Trans. Electron Comput. EC-13:14-17 (1964).
Dadda, L., "Some Schemes for Parallel Multipliers", Alta Freq. 34:349-356 (1965).
Dadda, L., "On Parallel Digital Multipliers", Alta Freq. 45:574-580 (1976).
HaL Computer Systems, Inc.
Mai Tan V.
Smith Albert C.
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