Method and apparatus for multiple row caches per bank

Static information storage and retrieval – Addressing – Plural blocks or banks

Reexamination Certificate

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C365S198000

Reexamination Certificate

active

06990036

ABSTRACT:
Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to write the data directed to at least one row through a write operation causing the data to written to the row of sense amplifiers versus from the row of memory cells, directly, and to store an indication that the data cached by the row of sense amplifiers is dirty.

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Katsumi Dosaka et al., “A 100-MHz 4-Mb Cache DRAM with Fast Copy-Back Scheme”, IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, XP 000320439, pp. 1534-1538.

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