Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-11-08
2004-06-08
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S042000
Reexamination Certificate
active
06747899
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory, and more particularly to nonvolatile semiconductor memory that is programmable as well as erasable.
2. Description of the Related Art
Nonvolatile memory retains stored data when power is removed, which is required or at least highly desirable in many different types of computers and other electronic devices. Some types of nonvolatile memory are capable of being repeatedly programmed and erased, including erasable programmable read only semiconductor memory generally known as EPROM, and electrically erasable programmable read only semiconductor memory generally known as EEPROM. EPROM memory is erased by application of ultraviolet light and programmed by application of various voltages, while EEPROM memory is both erased and programmed by application of various voltages. EPROMs and EEPROMs have suitable structures, generally known as floating gates, that are charged or discharged in accordance with data to be stored thereon. The charge on the floating gate establishes the threshold voltage, or V
T
, of the device, which is sensed when the memory is read to determine the data stored therein.
An illustrative well known type of compact floating gate EEPROM cell structure is the stacked gate structure shown in
FIG. 1. A
floating gate
14
, typically a doped polysilicon layer, is sandwiched between two insulator layers
12
and
16
, typically oxide. The top layer of the stack is a control gate electrode
10
, typically a doped polysilicon layer. The stacked gate structure is shown symmetrically overlying part of a heavily doped n+ source region
20
and a heavily doped n+ drain region
22
, as well as a channel region between the source region
20
and the drain region
22
. The channel region is part of a p-well
28
, which also contains the source region
20
, the drain region
22
, and a heavily p+ doped contact region
24
. The p-well
28
typically is contained within an n-type substrate or within an n-well such as shown at
30
, which also contains a heavily n+ doped contact region
26
. The n-well
30
is in turn contained in the p-type substrate
32
. Many variations in the floating gate EEPROM cell structure are known, and include asymmetrical stacked gate structures, split gate structures, and so forth. Moreover, although the structure of
FIG. 1
is an n-channel enhancement mode device, nonvolatile memory cells may be fabricated as either n-channel or p-channel devices or as enhancement or depletion mode devices.
As is typical of nonvolatile memory cells that are capable of being repeatedly programmed and erased, the various functions of the EEPROM stacked gate memory cell of
FIG. 1
are controlled by applying various bias voltages. The voltage applied to the control gate is V
G
, the voltage applied to the source is V
S
, the voltage applied to the drain is V
D
, the voltage applied to the p-well
28
is V
P
, the voltage applied to the n-well
30
is V
N
, and the voltage applied to the p-type substrate
32
is V
B
(not shown). Typically the substrate
32
is grounded, i.e. V
B
=0V. Typically writing or programming the memory cell means adding negative charge to the floating gate while erasing the memory cell means removing negative charge from the floating gate, but the charged state can be considered the erased state if desired. Other voltages are applied to read the charge state of the memory cell by detecting the threshold voltage V
T
of the memory cell, which ideally is done without disturbing the charge state.
Depending to some extent on device characteristics, the stacked gate transistor of
FIG. 1
may be programmed by moving electrons to the floating gate
16
using Fowler-Nordheim (“FN”) tunneling or electron injection. Electron injection typically is done using channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). CISEI is also known as substrate bias enhanced hot electron injection.
The EEPROM stacked gate memory cell of
FIG. 1
may be used in a variety of memory array architectures, including common ground arrays as well as virtual ground arrays. A memory is formed by combining a memory array with well known circuitry such as control logic, address decoders, sense amplifiers, and power supplies. An example of a memory
40
having an flash memory array
54
of such individual cells is shown in FIG.
2
. Various read, erase and program voltages are furnished by suitable power supplies (not shown). A serial memory address ADDR is latched into an address latch
44
, decoded for its row and column information (X and Y) by X decoder
48
and Y decoder
46
, and applied to the memory array
54
to access the selected row and column. If the operation is a program operation, the data to be written is temporarily stored in I/O buffer
50
as it is written to the memory array
54
. If the operation is a read, the selected bits are sensed by sense amplifier
52
and then temporarily stored in the I/O buffer
50
, where they are accessible to external circuits.
For many memory applications, one desires to read and program multiple bytes of the memory array
54
simultaneously, or even an entire page of the memory array
54
. Similarly, one may desire to erase multiple bytes or even an entire page of the memory array
54
at one time, or even multiple pages or the entire memory. To facilitate erasing, programming and reading multiple bytes or even an entire page, each row of the memory array or perhaps adjacent rows may correspond to a page of memory. A sector of memory may contain several pages. Such memory is known as “flash” memory because of the large number of bits that can be erased or programmed simultaneously.
One type of conventional flash memory uses FN tunneling for both erasure and programming. Unfortunately, programming using FN tunneling from the drain edge to the floating gate is relatively slow. Transistors using FN programming generally requires a longer channel length, leading to larger cell size. FN programmed memories also require bit-latch circuitry, which increases the size of the memory chip.
Another type of conventional flash memory uses CHE for programming. CHE programming is fast relative to FN programming. Unfortunately, the high drain voltage and programming current required by CHE renders the technique disadvantageous for use in low power applications, and severely limits the number of bits that can be programmed at one time. Simultaneous multiple byte programming is difficult to perform, as a practical matter.
While multiple byte programming and page mode programming of a CHE type memory can be achieved by repeated programming groups of bits until the desired amount of memory is programmed, the approach can result in an unfavorable condition known as program-disturb. Program-disturb is related to the voltage conditions that occur in the part of the memory that is not being programmed while another part of the memory is being programmed. These voltage conditions cause multiple minute shifts in the threshold voltage of the memory cells that are not being programmed, which occur as other parts of the memory are being programmed. A similar problem occurs during read-out of data. Read voltages applied to the nonvolatile cells, including both the addressed cells and some of the cells that are not addressed, can induce a threshold voltage shift in these cells. While program-disturb and read-disturb can be avoided by the use of an isolating select transistor in each memory cell, such transistors are undesirable insofar as they cause an increase in the size of the memory cell and a corresponding decrease in the memory array density.
A technique is known that uses negative substrate biasing of the flash memory cells to overcome some of the disadvantages of conventional CHE. An example of this technique is disclosed in U.S. Pat. No. 5,659,504, which issued Aug. 19, 1997, to Bude et al. and is entitled “Method and Apparatus for Hot Carrier Injection.”The Bude et al. p
Han Kyung Joon
Hsia Steve K.
Tran Dung
Altera Law Group LLC
Ho Hoai
NexFlash Technologies, Inc.
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