Electrical computers and digital processing systems: processing – Processing architecture – Vector processor
Patent
1998-03-31
2000-04-18
Coleman, Eric
Electrical computers and digital processing systems: processing
Processing architecture
Vector processor
710 68, G06F 1580
Patent
active
060527692
ABSTRACT:
A method comprises decoding a single instruction having a first operand identifying a plurality of bytes of packed data and a second operand identifying a corresponding plurality of byte masks. Each of the plurality of byte masks identified by the second operand of the single decoded instruction are analyzed, wherein select bytes of the plurality of bytes identified by the first operand are moved to an implicitly defined location based, at least in part, on the analysis of the individual byte masks identified by the second operand of the single decoded instruction.
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Hoffman Nathaniel
Huff Thomas R.
Thakkar Shreekant
Coleman Eric
Intel Corporation
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