Method and apparatus for moving data in a parallel processor usi

Details Method and apparatus for moving data in a parallel processor usi Method and apparatus for moving data in a parallel processor usi

1997-07-10

2000-07-11

Ellis, Richard L.

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

G06F 1500

Patent

active

060887826

ABSTRACT:
A Single Instruction Multiple Data processor apparatus for implementing algorithms using sliding window type data is shown. The implementation shifts the elements of a Destination Vector Register (406, 606) either automatically every time the destination register value is read or in response to a specific instruction (800). The shifting of the Destination Vector Register (406, 606) allows each processing element to operate on new data. As the destination vector (406, 606) elements are shifted, a new element is provided to the vector from a Source Vector Register (404, 604).

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Howe's Free On-line Dictionary of Computing (http://www.instantweb.com/.about.foldoc/), mnemonic, instruction mnemonic, op code, modulo, Feb. 1997.
A scalar architecture for pseudo vector processing based on slide-windowed registers; Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, and Yoshiyuki Yamashita; Supercomputing; http://www.acm.org, 1993.
Chen, et al., "Introduction to Computer Architecture", Science Research Associates, Inc., pp. 326-355 (1975).

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