Method and apparatus for monotonic algorithmic digital-to-analog

Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion

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341172, H03M 166, H03M 112

Patent

active

052587592

ABSTRACT:
The present invention provides a compact and robust architecture and a corresponding method to implement a monotonic algorithmic D/A converter that processes the bits of the digital input in the order from MSB to LSB, and a successive approximation A/D converter employing the intermediate conversion results of this D/A converter. The invention is aimed at applications requiring a dense integration in general VLSI technologies of multiple D/A and A/D converters, where individual trimming of components to compensate for component offsets and mismatches is virtually impossible. The architecture comprises four charge holding components, one switch for charge sharing, two bi-directional replication elements for charge storage and recall, and one comparator. Also described is an efficient way of performing pseudo-logarithmic compression of conversion values merely by adjusting the relative sizes of two of the charge holding components.

REFERENCES:
patent: 4065766 (1977-12-01), Butler et al.
patent: 4070667 (1978-01-01), Eichelberger
patent: 4072939 (1978-02-01), Heller et al.
patent: 4144526 (1979-03-01), Wotruba

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