Method and apparatus for monitoring wafer stress

Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed

Reexamination Certificate

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Details

C438S014000, C438S007000, C716S030000

Reexamination Certificate

active

06509201

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor manufacturing, and, more particularly, to a method and apparatus for monitoring film stress during a semiconductor manufacturing process.
2. Description of the Related Art
The technology explosion in the manufacturing industry has resulted in many new and innovative manufacturing processes. Today's manufacturing processes, particularly semiconductor manufacturing processes, call for a large number of important steps. These process steps are usually vital, and therefore, require a number of inputs that are generally fine tuned to maintain proper manufacturing control.
The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.
Among the factors that affect semiconductor device manufacturing are wafer-to-wafer variation that are caused by manufacturing problems that include start-up effects of manufacturing machine tools, memory effects of manufacturing chambers, and first-wafer effects. One of the process steps that is adversely affected by such factors is the photolithography overlay process. Overlay is one of several important steps in the photolithography area of semiconductor manufacturing. Overlay control involves measuring the misalignment between two successive patterned layers on the surface of a semiconductor device. Generally, minimization of misalignment errors helps ensure that the multiple layers of the semiconductor devices are connected and functional. As technology facilitates smaller critical dimensions for semiconductor devices, the need for reduced misalignment errors increases dramatically.
Generally, a set of processing steps is performed on a lot of wafers on a semiconductor manufacturing tool called an exposure tool or a stepper. The manufacturing tool communicates with a manufacturing framework or a network of processing modules. The manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which the stepper is connected, thereby facilitating communications between the stepper and the manufacturing framework. The machine interface can generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process. The input parameters that control the manufacturing process are revised periodically in a manual fashion. As the need for higher precision manufacturing processes are required, improved methods are needed to revise input parameters that control manufacturing processes in a more automated and timely manner. Furthermore, wafer-to-wafer manufacturing variations can cause non-uniform quality of semiconductor devices.
A known technique for evaluating the acceptability of the photolithography and other processes involves measuring critical dimensions or other parameters after the process is performed. However, variations in film stress on a semiconductor wafer can reduce the accuracy of measurements. Furthermore, variations in film stress can reduce the predictability of the compensation steps that are taken to reduce errors in manufacturing processes.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for characterizing wafer stress. At least one semiconductor device is processed. Metrology data from the processed semiconductor device is acquired. Micro-Raman data relating to the processed semiconductor device is acquired. A wafer-stress analysis based upon the metrology data and the micro-Raman data is performed. A feedback process based upon the wafer stress analysis is performed.
In another aspect of the present invention, a system is provided for characterizing wafer stress. The system of the present invention comprises: a computer system; a manufacturing model coupled with the computer system, the manufacturing model being capable of generating and modifying at least one control input parameter signal; a machine interface coupled with the manufacturing model, the machine interface being capable of receiving process recipes from the manufacturing model; a processing tool capable of processing semiconductor wafers and coupled with the machine interface, the first processing tool being capable of receiving at least one control input parameter signal from the machine interface; a metrology tool coupled with the first processing tool and the second processing tool, the metrology tool being capable of acquiring metrology data; a metrology data analysis unit coupled with the metrology, the metrology data analysis unit being capable of organizing the acquired metrology data; a micro-Raman data acquisition unit coupled to the processing tool, the micro-Raman data acquisition unit being capable of acquiring micro-Raman data relating to the semiconductor wafers; and a correlator coupled to the micro-Raman data acquisition unit and the metrology data analysis unit, the correlator being capable of consolidating the metrology data and the micro-Raman data to perform a corrective feedback function for a manufacturing process based upon a wafer stress calculation performed using the consolidated data.


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