Semiconductor device manufacturing: process – Including control responsive to sensed condition – Optical characteristic sensed
Reexamination Certificate
2000-01-24
2001-05-15
Powell, William (Department: 1765)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
Optical characteristic sensed
C156S345420, C216S059000, C438S014000, C438S710000
Reexamination Certificate
active
06232134
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to semiconductor manufacturing, and more particularly to using charge distribution patterns collected from semiconductor wafers to monitor wafer processing consistency and/or accuracy and qualify IC processes.
BACKGROUND OF THE INVENTION
Integrated circuits are typically formed on a substrate such as a silicon wafer using a number of processing steps. Such processing steps include steps such as etching steps that remove selected portions of material deposited on the wafer. In order to consistently produce functional integrated circuits, the processing steps such as etching steps must be performed in a consistent manner.
In order to monitor process step characteristics such as etching rates, prior art systems often required patterned test wafers to be processed and then cross-sectioned to determine how the processing steps are currently being performed. In one prior art system, different portions of the wafer are isolated through cross-sectioning and manually measured using devices such as micrometers in order to determine the rate of etching. Such prior art systems require intense manual operations that are time consuming and inefficient. In addition to this drawback, such prior art systems often only provide data for isolated portions of the overall wafer such that a complete view of the performance of the processing operation with respect to the entire wafer is not achieved.
Other prior art systems utilized large via holes (on the order of 0.5 micron) which are visually examined after processing to determine etching rates. Because actual geometries of circuit elements in integrated circuits processed based on current technology are significantly smaller than the fairly large geometries associated with the via holes used for visual inspection, the etching rate may not be accurately determined for the smaller geometry features. This is because features having larger geometries are often etched at a rate that differs significantly than that for features of smaller geometries. In other words, the rate of etching in a large gap may occur at a faster rate than the etching rate in smaller gaps. This prior art technique also suffers from requirement that manual measurements must be performed, thus increasing the cost associated with the process and reducing both accuracy and practicality.
Other prior art systems included a special layer such as a titanium nitride layer below the material being etched. If, following the etching process, the special layer had not been reached, a visual inspection would reveal that the etching rate was less than expected. If the special layer could be visually observed following etching, it could be determined that the etching rate was sufficient to etch through the amount of material overlying the special layer. Unfortunately, such a coarse level of etch rate analysis is often inadequate to accurately characterize the etching rate to a point that it is beneficial promoting proper processing operations.
Each of the prior art techniques discussed thus far are time consuming to the point where they are often performed on an infrequent basis. In some cases, the etching rate would only be monitored on a bi-weekly basis. As such, problems that arose between points of measurement could persist for days without corrective measures being taken. Because wafers are often processed at a high rate in factories that operate around the clock, this could result in a significant number of faulty integrated circuits being produced.
As is known in the art, charge measurement instruments have been designed for measuring charge distributions on the surface of a wafer. Such charge distributions are often a result of processing steps that cause a static charge to be built up on the surface of the wafer. Such a static charge can be measured through a measurement based on capacitance that determines the charge distribution across the surface of the wafer. Although such charge monitoring capacity is currently known, it has only been used to monitor damage that may have been induced to various structures and the integrated circuits due to charge gradients or concentrations.
Therefore, a need exists for a method and apparatus for monitoring performance of processing steps such as etching rates in a manner that requires less manual interaction, produces more accurate results, and which can be performed in a fast and efficient manner such that more frequent monitoring can be performed in a cost effective manner.
REFERENCES:
patent: 4859277 (1989-08-01), Barna et al.
patent: 6054333 (2000-04-01), Bensaoula
patent: 6060329 (2000-05-01), Kamata et al.
Crabtree Phillip E.
Farber David Gerald
Wu Wei E.
Motorola Inc.
Powell William
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