Method and apparatus for monitoring SOI hysterises effects

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor

Reexamination Certificate

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Details

C324S765010, C368S113000, C368S118000

Reexamination Certificate

active

06239591

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to integrated circuit fabrication and test methodologies, and, particularly, to a novel method and system for in-line monitoring of hysteresis effects exhibited by silicon-on-insulator (SOI) wafer manufacturing process.
2. Discussion of the Prior Art
It is commonly known that the SOI floating body results in hysterises effects whereby the delay through a set of SOI circuits depends on the input history. Manufacturing control of this history effect is critical. Methods to measure SOI hysteresis effects are readily available, but require the use of high speed measurement equipment and high-frequency test probes that are not amenable to inline manufacturing high-throughput and inexpensive testing/monitoring/characterization.
It would be highly desirable to provide an SOI hysteresis test structure that eliminates the need for non-standard, high-frequency inline test equipment and test probes.
Moreover, it would additionally be highly desirable to provide an SOI hysteresis test structure that may be wholly implemented within the kerf of the chip, separate from other active chip circuits.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an apparatus and test methodology that measures the history effect associated with a floating body in a manufacturing environment. The SOI hysteresis test structure eliminates the need for non-standard inline test equipment, and moreover, may be wholly implemented within the kerf of the chip. Furthermore, the test technique may be implemented with standard voltmeters, for instance, and is simple and efficient to carry out providing for higher wafer throughput.
In this invention, a first switch delay through a long chain of SOI inverters that has been in a “DC” state for every long time is compared to the “steady state” delay through a short SOI inverter ring oscillator. The difference in the DC and steady state delays bound the hysterises effects for the inverter circuits. The two delays are compared via an on-chip counter, eliminating the need for high-speed test equipment or probe sets.
According to the principles of the invention, there is provided an apparatus and method for measuring hysteresis effects of a wafer process, the method comprising: generating a pulse having a pulse width equal to the delay of a transition through a delay chain wherein the delay chain has been in a static condition for a substantial length of time; counting a number of oscillations from a ring oscillator generated during the pulse width wherein the ring oscillator has been operating in a steady state condition; comparing the number of oscillations with an expected value; and correlating a difference resulting from the comparing step with a level of hysteresis effected by the wafer process.


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patent: 5995011 (1999-10-01), Kurihara et al.

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