Method and apparatus for modifying two's complement multiplier t

Details Method and apparatus for modifying two's complement multiplier t Method and apparatus for modifying two's complement multiplier t

1990-08-24

1992-10-06

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

051538504

ABSTRACT:
A two's complement multiplier is combined with additional circuit elements and implemented in an integrated circuit to provide a multiplier of selectively operating in two's complement or unsigned magnitude format. To achieve an unsigned magnitude product, the additional circuitry modifies or leaves unchanged the high-order half of the two's complement product as needed. Modification occurs when the most-significant bit of either or both multiplicand signals is a "1". When a multiplicand signal has a most-significant bit of "1", the non-most significant bits of the other multiplicand signal are added to the two's complement product to derive the unsigned magnitude product. Such an implementation results in insignificant speed loss and comparatively minor increase in the required silicon area.

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patent: 4868778 (1989-04-01), Disbrow
Booth, Andrew D., "A Signed Binary Multiplication Technique", Computer Design Development, pp. 163-166.
Garner, Harvey L., "The Residue Number System", Computer Design Development, pp. 181-192.
Dadda, L., "Some Schemes for Parallel Multipliers", Computer Design Development, pp. 167-180.
Gosling, John B., "Design of Arithmetic Units for Digital Computers", pp. 22-38.

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