Data processing: software development – installation – and managem – Software program development tool – Translation of code
Reexamination Certificate
1999-06-29
2001-11-20
Coleman, Eric (Department: 2183)
Data processing: software development, installation, and managem
Software program development tool
Translation of code
C717S152000, C712S032000
Reexamination Certificate
active
06321380
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates in general to data processing systems and in particular to a processor (processor) in a data processing system. More particularly, the present invention relates to instruction operations within the processor.
2. Description of the Related Art
Complex processors have very little room for performance errors and typically must operate with little or no processing errors. During initial design stages of a complex processor, it is probable that program instructions will have to be modified to improve operations that have a direct effect on performance. Additionally, performance errors may be found, in the field in program designs after a processor has been installed.
Many complex processors utilize a reduced instruction set computer (“RISC”) core processor which is generally characterized by high throughput of instructions. RISC processors usually operate at a high clock frequency and because of the minimal instruction set do so very efficiently. In addition to high clock speed, processor efficiency is improved even more by the inclusion of multiple execution units allowing the execution of two, and sometimes more, instructions per clock cycle.
Processors with the ability to execute multiple instructions per clock cycle are described as “superscalar.” Superscalar processors, such as the PowerPC™ family of processors available from IBM Corporation of Armonk, N.Y., provide simultaneous dispatch of multiple instructions. Included in the processor are an Instruction Cache (“IC”), an Instruction Dispatch Unit (“IDU”), an Execution Unit (“EU”) and a Completion Unit (“CU”). Generally, a superscalar, RISC processor is “pipelined,” meaning that a second instruction is waiting to enter the execution unit as soon as the previous instruction is finished. A typical RISC instruction set (PowerPC™) contains three broad categories of instructions: branch instructions (including specific branching instructions, system calls and Condition Register logical instructions); fixed point instructions and floating point instructions. Each group is executed by an appropriate function unit.
In a superscalar processor, instruction processing is usually accomplished in six stages—fetch, decode, dispatch, execute, completion and writeback stages. The fetch stage is primarily responsible for fetching instructions from an instruction cache and determining the address of the next instruction to be fetched. The decode stage generally handles all time-critical instruction decoding for instructions in an instruction buffer. The dispatch stage is responsible for non-time-critical decoding of instructions supplied by the decode stage and for determining which of the instructions can be dispatched in the current cycle.
The execute stage executes the instruction selected in the dispatch stage, which may come from the reservation stations or from instructions arriving from dispatch. The completion stage maintains the correct architectural machine state by considering instructions residing in a completion buffer and utilizes information about the status of instructions provided by the execute stage. The write back stage is used to write back any information from rename buffers that is not written back by the completion stage.
Complex processors, in this instance utilizing a RISC core, must perform with little or no margin for error. Instructions must be transformed into one or more internal operations (read hardware instructions) in the Instruction Decode Unit. At different stages between initial design and field experience, originally designed instruction operations in the processor may be changed because of unforeseen problems. Generally, the process requires a determination of the operation(s) that needs to be modified, a redesign of the hardware instructions and a reprogram of the processor. If errors are found in the field, the modification of the system is much more expensive in time and money. Generally, the processor must be changed out and any required support devices must be reprogrammed or changed out, contributing to an unnecessary expense in time and money. Furthermore, any advances made in the chip firmware currently requires that the chip be replaced.
It would be desirable therefore, to provide a method and apparatus that would allow for substituting instruction operations, both in the field and in the design stage, that would optimize performance and flexibility of a processor. It would also be desirable to provide a mechanism that would recognize incorrect instructions and enable correction of the instructions.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide a method and apparatus that will modify incorrect instructions in a processor.
It is another object of the present invention to provide a method and apparatus that will identify instructions in a processor that require modification.
It is yet another object of the present invention to provide a method and apparatus that will modify hardwired code in a processor.
The foregoing objects are achieved as is now described. A “soft-patch” allows an instruction or group of instructions to be replaced with a pre-loaded instruction or group of instructions. When an Instruction Fetch Unit (IFU) fetches an instruction, the instruction is sent through a Compare and Mask (CAM) circuit which masks and compares, in parallel, the instruction with up to eight pre-defined masks and values. The masks and values are pre-loaded by a service processor to CAM circuits which are located in an Instruction Dispatch Unit (IDU) and the IFU in the central processor. An instruction that is deemed a match, is tagged by the IFU as a “soft-microcode” instruction. When the IDU receives the soft-microcode instruction for decoding, it detects the soft microcode marking and sends the marked instruction to a soft-microcode unit; a separate parallel pipeline in the IDU. The soft-microcode unit then sends the instruction through a CAM circuit which returns an index (or address) for RAM. The index is used to read values out of IDU RAM and generate replacement instructions. Additionally, an Internal Operation that will cause the processor core to perform an unconditional branch to a fixed real address, can be loaded into the IDU RAM allowing an instruction to be replaced by a subroutine or handler routine contained outside the processor core.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5748978 (1998-05-01), Narayan
patent: 5794063 (1998-08-01), Favor
patent: 5862370 (1999-01-01), Dockser
patent: 5884058 (1999-03-01), Narayan
patent: 6049672 (2000-04-01), Shiell
patent: 6135651 (2000-10-01), Leinfelder
patent: 6141740 (2000-10-01), Mahalingaiah
patent: 6230258 (2001-05-01), Takayama
Derrick John Edward
Eisen Lee Evan
Reick Kevin Franklin
Bracewell & Patterson L.L.P.
Coleman Eric
England Anthony V. S.
International Business Machines - Corporation
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