Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-07-13
2002-06-25
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S641000, C156S345420
Reexamination Certificate
active
06410351
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor device manufacturing, and, more particularly, to a method and apparatus for modeling the thickness profile of a deposition tool, such as a diffusion furnace, and controlling a subsequent etch process.
2. Description of the Related Art
In the manufacture of semiconductor devices, wafers, such as silicon wafers, are subjected to a number of processing steps. The processing steps include depositing or forming layers, patterning the layers, and removing portions of the layers to define features on the wafer. One such process used to form the layers is known as chemical vapor deposition (CVD), wherein reactive gases are introduced into a vessel, e.g., a CVD tool, containing the semiconductor wafers. The reactive gases facilitate a chemical reaction that causes a layer to form on the wafers. One exemplary deposition process is the formation of polysilicon by reacting nitrogen (N
2
) and silane (SiH
4
) in a furnace.
There are many factors that affect the deposition rate of a deposition tool. These factors include, among other things, the flow rate of reactive gases through the chamber and the temperature of the chamber. Typically, to determine the deposition rate for a particular tool (e.g, when it is first placed in service or after a maintenance event), a series of qualification wafers are processed and the resultant thickness of the process layer is measured. The measurements are used to estimate the deposition rate of the tool. Deposition times for subsequently processed wafers are determined based on the anticipated deposition rate. Normal variations in temperature and reactant flow rate may cause a deviation in the deposition rate from the anticipated rate, causing the process to exceed a control limit.
A typical deposition tool, such as a vertical furnace, processes a multiple lots of wafers simultaneously (e.g., 50 or more wafers). The wafers are placed in a carrier and inserted into the furnace. Typically, the reactive gases that are used to form the process layer are introduced into the bottom of the furnace. As the reactive gases circulate toward the top of the furnace, the A concentrations of the reactive gases decrease (i.e., the reactive gases are consumed in forming the process layers on the lower wafers). This decreased concentration results in a lower deposition rate as the distance from the gas inlet increases. To address this situation, the furnace is divided into zones (e.g., 4 zones) and the temperature of each zone is controlled independently. The zones nearer the top of the furnace are controlled at a higher temperature than those nearer the bottom to increase their localized deposition rates.
Although the approach described above tends to normalize the average deposition rate across the zones, is does not address thickness variations within a zone. Subsequent etch tools can be configured to etch the process layer based on the average deposition rate, but variations present in the wafers processed in a particular zone will propagate through the etch process, resulting in variations in the post-etch characteristics (i.e., the layers may be over-etched or under-etched). Process variations can result in reduced equipment utilization and availability. Generally, a greater process variation results in a more costly and less efficient processing system.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a processing line including a deposition tool, a metrology tool, an etch tool, and a process controller. The deposition tool is adapted to form a process layer on a plurality of wafers. The metrology tool is adapted to measure the thickness of the process layer for a sample of the wafers. The etch tool is adapted to etch the process layer in accordance with an operating recipe. The process controller is adapted to store a thickness profile model of the deposition tool, generate predicted process layer thicknesses for the wafers not measured by the metrology tool based on the process layer thickness measurements of the wafers in the sample and the thickness profile model, and modify the operating recipe of the etch tool based on the predicted process layer thicknesses.
Another aspect of the present invention is seen in a method for controlling wafer uniformity. The method includes storing a thickness profile model of a deposition tool; depositing a process layer on a plurality of wafers in the deposition tool; measuring the thickness of the process layer for a sample of the wafers; generating predicted process layer thicknesses for the wafers not measured based on the process layer thickness measurements and the thickness profile model; and etching the process layer in an etching tool in accordance with an operating recipe, the operating recipe being based on the predicted process layer thicknesses.
REFERENCES:
patent: 6133132 (2000-10-01), Toprac
patent: 6161054 (2000-12-01), Rosenthal
patent: 6298470 (2001-10-01), Breiner
Bode Christopher A.
Toprac Anthony J.
Advanced Micro Devices , Inc.
Stevenson André C
Williams Morgan & Amerson P.C.
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