Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Event-driven
Reexamination Certificate
2004-10-14
2008-12-02
Shah, Kamini (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Event-driven
C709S248000, C712S008000, C712S009000, C712S022000, C712S023000, C713S400000, C713S600000, C714S011000, C714S012000, C714S707000, C714S741000
Reexamination Certificate
active
07460989
ABSTRACT:
A method is provided, wherein a virtual internal master clock is used in connection with a RISC CPU. The RISC CPU comprises a number of concurrently operating function units, wherein each unit runs according to its own clocks, including multiple-stage totally unsynchronized clocks, in order to process a stream of instructions. The method includes the steps of generating a virtual model master clock having a clock cycle, and initializing each of the function units at the beginning of respectively corresponding processing cycles. The method further includes operating each function unit during a respectively corresponding processing cycle to carry out a task with respect to one of the instructions, in order to produce a result. Respective results are all evaluated in synchronization, by means of the master clock. This enables the instruction processing operation to be modeled using a sequential computer language, such as C or C++.
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Doudnikoff Gregory M.
International Business Machines - Corporation
Patel Shambhavi
Shah Kamini
Skarsten James O.
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