Method and apparatus for modeling an integrated circuit in a...

Details Method and apparatus for modeling an integrated circuit in a... Method and apparatus for modeling an integrated circuit in a...

2008-10-29

2011-11-22

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Physical design processing

C716S112000

Reexamination Certificate

active

08065648

ABSTRACT:
Method, apparatus, and computer readable medium for modeling an integrated circuit in a computer aided design system (CAD) are described. In some examples, a device model of the integrated circuit is generated in at least one first computer file, the device model having a component hierarchy. A common delay identifier is defined for component instances in the component hierarchy of the device model. A value model is generated for the device model in at least one second computer file. Delay values are defined for the common delay identifier in the value model, at least a portion of the delay values being qualified based on location in the component hierarchy of at least one of the component instances.

REFERENCES:
patent: 6820245 (2004-11-01), Beattie et al.
patent: 6828963 (2004-12-01), Rappoport
patent: 7454732 (2008-11-01), McElvain et al.
patent: 7788614 (2010-08-01), Galloway et al.

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