Coded data generation or conversion – Digital code to digital code converters
Reexamination Certificate
2006-10-31
2006-10-31
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
C380S046000
Reexamination Certificate
active
07129859
ABSTRACT:
Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.
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Benini, L. et al.; Energy-efficient data scrambling on memory-processor interfaces;□□Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED ′03. □□Aug. 25-27, 2004 pp. 26-29.
Dreps Daniel M.
Reese Robert J.
Saenz Hector
Frankeny Richard F.
International Business Machines - Corporation
Williams Howard L.
Winstead Sechrest & Minick P.C.
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