Method and apparatus for minimizing phase error and jitter...

Details Method and apparatus for minimizing phase error and jitter... Method and apparatus for minimizing phase error and jitter...

2007-07-10

2007-07-10

Pascal, Robert (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S017000, C331S025000, C331S00100A, C327S157000, C327S536000

Reexamination Certificate

active

11120914

ABSTRACT:
An apparatus that minimizes phase error and jitter in a phase-locked loop. The apparatus includes a phase/frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider, which are coupled together to form a phase-locked loop. The charge pump within the phase-locked loop contains a pull-up network and a pull-down network which are coupled to each other, and a current compensation device. If the pull-up network and the pull-down network are both conducting, the current compensation device adjusts currents flowing through the pull-up network and through the pull-down network such that the currents are substantially equal. This ensures that very little current flows into the loop filter, thereby substantially minimizing a build-up of charge on a capacitor in the loop filter, which can cause phase error and jitter in the phase-locked loop.

REFERENCES:
patent: 3898579 (1975-08-01), Aldridge
patent: 5508660 (1996-04-01), Gersbach et al.
patent: 6118346 (2000-09-01), Olgaard
patent: 6570421 (2003-05-01), Gauthier et al.
patent: 2003/0048126 (2003-03-01), Watarai
patent: 2004/0257162 (2004-12-01), Mokeddem
Publication: “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques”, by John G. Maneatis, IEEE Journal of Solid-Site Circuits, vol. 31, No. 11, Nov. 1996, pp. 1723 to 1732.

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