Method and apparatus for merging hierarchical test subsequence a

Details Method and apparatus for merging hierarchical test subsequence a Method and apparatus for merging hierarchical test subsequence a

1995-03-06

1997-05-13

Beausoliel, Jr., Robert W.

Excavating

371 27, G01R 3128

Patent

active

056300514

ABSTRACT:
Hierarchical Test Subsequence (TS) subgraphs and Finite State Machine (FSM) subgraphs are merged.
Hierarchical FSM subgraphs are merged (82) by connecting FSM model (33) child subgraph transitions or graph edges with states or vertices in the FSM parent subgraph. Matching is done based on Input/Output sequences. This merging (82) is repeated until all FSM child subgraphs are merged into FSM childless subgraphs. FSM childless subgraphs are Merged FSM graphs (83).
Hierarchical Test Subsequence (TS) subgraphs (65) are merged (38) by finding peer subgraphs for TS child subgraphs. TS micro-edges from module entry and to module exit are connected to peer level FSM model states or vertices identified by matching Input/Output sequences. This merging (38) is repeated until all TS child subgraphs are merged into TS childless subgraphs. TS childless subgraphs are Merged TS graphs (39).

REFERENCES:
patent: 4692921 (1987-09-01), Dahbura et al.
patent: 4991176 (1991-02-01), Dahbura et al.
patent: 5228040 (1993-07-01), Agrawal et al.
patent: 5394347 (1995-02-01), Kita et al.
patent: 5426651 (1995-06-01), Van De Burgt
patent: 5452215 (1995-09-01), Washabaugh
patent: 5459841 (1995-10-01), Flora-Holmquist et al.
Thomas H. Cormen et al., Introduction to Algorithms, 1985 MIT Press, Cambridge, Mass.
Alfred V. Aho, et al., An Optimization Technique for Protocol Conformance Test Generation . . . Protocol Specification Testing and Verification VIII, p. 75, IFIP 1988.
Anton Dahbura et al., An Optimal Test Sequence for the JTAG/IEEE p. 1149.1 Test Access Port Cntlr. IEEE Proceedings 1989 International Test Conference, pp. 55-62, 1989.
Xiao Sun et al., Protocol Conformance Testing by Discriminating UIO Sequences Protocol Specification Testing and Verification XI, p. 349, IFIP 1991.
Xiao Sun et al., On the Verification and Validation of Protocols with High Fault Coverage Using UIO Seq IEEE, 1992.
Kwang-Ting Cheng et al., Automatic Functional Test Generation Using the Finite State Machine Model 30th ACM/IEEE Design Automation Conference, p. 86, 1993.
Xiao Sun, Automatic Conformance Testing of Protocols Implemented in Software and Hardware Ph.D. Dissertation, Texas A&M University, Aug. 1993.

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