Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2011-08-16
2011-08-16
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S100000, C716S108000
Reexamination Certificate
active
08001505
ABSTRACT:
An electronic design automation technology merges coverage logs. The coverage logs are generated by verification of a hardware description language circuit design. The coverage logs are merged as the coverage logs are generated, without waiting for all pending coverage logs. Another electronic design automation technology also merges coverage logs. The merged coverage logs include a first coverage log of a first simulation of a hardware description language circuit design and a second coverage log of a second simulation of the hardware description language circuit design. The first simulation is based on a first hardware verification language coverage model of the hardware description language circuit design. The second simulation is based on a second hardware verification language coverage model of the hardware description language circuit design. The second hardware verification language coverage model is newer and different than the first hardware verification language coverage model.
REFERENCES:
patent: 6718521 (2004-04-01), Bentlage et al.
patent: 2004/0154002 (2004-08-01), Ball et al.
patent: 2004/0225973 (2004-11-01), Johnson
patent: 2008/0147373 (2008-06-01), Roessler et al.
Michael Koch “Distributed VHDL Simulation Within a Workstation Cluster,” Proceedings of the 27th Annual Hawaii International Conference on System Sciences, vol. II: Software Technology, pp. 313-322, Jan. 4-7, 1994.
International Search Report mailed Mar. 16, 2010 for a PCT Family Member Application No. PCT/US2009/052354, 11 pages.
Bist Manoj
Mehrotra Sandeep
Dimyan Magid Y
Haynes Beffel & Wolfeld LLP
Siek Vuthe
Suzue Kenta
Synopsys Inc.
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