Method and apparatus for merging binary translated basic blocks

Details Method and apparatus for merging binary translated basic blocks Method and apparatus for merging binary translated basic blocks

1996-06-27

2000-08-15

Vu, Viet D.

Electrical computers and digital processing systems: processing

Instruction decoding

712214, 395705, G06F 930

Patent

active

061051241

ABSTRACT:
A method for merging binary translated basic blocks of instructions. The method is for use in a computer system having in a memory a first set of instructions including blocks of instructions, and a translator for translating instructions executable on a source instruction set architecture into instructions executable on a target instruction set architecture. The method includes a first step of determining, by the translator, an order of execution from a first block of instructions to a second block of instructions. A second step of the method includes generating, by the translator, a hyperblock of instructions representing the first and second block of instructions translated and placed adjacent in a memory location in the order of execution.

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