Method and apparatus for memory interleaving using an improved h

Details Method and apparatus for memory interleaving using an improved h Method and apparatus for memory interleaving using an improved h

1991-06-18

1994-12-27

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 364DIG2, G06F 1200

Patent

active

053773403

ABSTRACT:
A novel memory hashing system is disclosed. The system converts an address into a hashed address of the form (B,C) where B is a module number in a multi-module memory system and C is an offset in the module. The system can be shown to have no pathological cases for any stride value less than some predetermined value. An apparatus according to the present invention is conveniently implemented in a pipelined architecture which allows one address value to be calculated each memory cycle. The present invention utilizes a special matrix calculated from a primitive polynomial for calculating the hashed addresses. The conversion of any given address requires one row of the matrix. The entries of the matrix may be stored in ROM. Alternatively, the required row of the matrix may be calculated in response to receiving the address which is to be convened to the hashed address.

REFERENCES:
patent: 5111389 (1992-05-01), McAuliffe et al.
patent: 5133061 (1992-07-01), Melton et al.
patent: 5134695 (1992-07-01), Ikeda
patent: 5247645 (1993-09-01), Mirza et al.

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