Method and apparatus for memory device wordline

Details Method and apparatus for memory device wordline Method and apparatus for memory device wordline

2006-05-16

2006-05-16

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S051000, C365S063000

Reexamination Certificate

active

07046578

ABSTRACT:
A method and apparatus for improving the speed of a wordline in a memory device. A wordline structure includes a main wordline for selectively distributing a main wordline signal and a plurality of wordlines selectively coupled to the main wordline. Each of the wordlines is selectively coupled to a lower resistivity shared interconnection line by way of a selected one of a plurality of switching elements each commonly coupled on one end to the shared interconnection line and individually coupled on an opposing end to the plurality of wordlines. Each of the plurality of switching elements is selectively activated to couple one of the plurality of wordlines to the shared interconnection line when the main wordline signal is selectively coupled to one of the plurality of wordlines.

REFERENCES:
patent: 5587960 (1996-12-01), Ferris
patent: 5761149 (1998-06-01), Suzuki et al.
patent: 6330205 (2001-12-01), Shimizu et al.
patent: 6556503 (2003-04-01), Schreck
patent: 6953960 (2005-10-01), Tomishima
patent: 2002/0153545 (2002-10-01), Tomishima

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