Static information storage and retrieval – Addressing – Byte or page addressing
Reexamination Certificate
1999-12-29
2001-06-26
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Addressing
Byte or page addressing
C365S238500, C365S233100, C345S520000
Reexamination Certificate
active
06252821
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to data communications in a computer system, and more specifically, to decoding of memory access addresses to produce memory device signals.
2. Background Information
Computer systems generally include at least a central processing unit and a memory subsystem that stores instructions and data to be used by the central processing unit. Many computer systems will also include other subsystems, such as input/output subsystems, that can also read and write data from the memory subsystem. In a flat memory architecture, the memory subsystem is accessed as a collection of data units each of which has a unique address.
Most memory devices cannot directly receive a memory access address as presented by the central processing unit. Therefore, the memory subsystem includes a memory controller that provides a bridge between the memory devices and the other portions of the computer system.
One function of the memory controller is to receive the memory access address directed to the memory subsystem and the decode the memory access address to produce the address signals as required by the memory devices. The size of the memory subsystem is often larger than the size of a single memory device in the memory subsystem. Therefore, part of the memory access address is used to select a particular memory device within the memory subsystem and another part of the memory access address is used to select a data unit from within the memory device.
The memory subsystem must be able to respond to memory access requests quickly to avoid slowing down the central processing unit and other subsystems within the computer system. This requires that a memory access address be quickly decoded to produce the necessary signals to access the requested data unit from the appropriate memory device. One aspect of the decoding process is determining the memory device that contains the requested data unit. This is necessary not only to generate the necessary signals to access the appropriate memory device but also to determine what addressing signals are required to access the data unit within the selected memory device. A memory subsystem may contain a variety of memory devices with different sizes, different organizations of data units, and different addressing requirements.
In some prior art memory subsystems, boundary address registers are used to determine the memory device that contains the requested data unit. The prior art memory subsystems are generally limited to having eight or fewer memory devices. Thus the number of boundary address registers required was also limited to eight or less.
Demands for increasingly larger memory subsystems have led to designs, such as the Direct Rambus™ memory channel architecture, that can include a much larger number of memory devices than the prior art memory subsystems. For example, a Direct Rambus™ memory channel can have up to 32 memory devices. A single memory subsystem can include multiple memory channels increasing the number of memory devices even further. If a data boundary register is provided for every possible memory device in a memory subsystem that supports a large number of memory devices, the decode logic will take a significant length of time to identify the memory device.
SUMMARY
One embodiment of the invention is a method for decoding a memory access address. A portion of the memory access address is compared to a plurality of boundary values, each of the plurality of boundary values representing an uppermost address for a group of memory devices, each of the memory devices in the group having the same configuration. A group number is generated that represents an addressed group that contains an addressed memory device that contains the memory access address. A device number is generated that represents the location of the addressed memory device within the addressed group. A device selection signal is generated responsive to the group number and the device number.
REFERENCES:
patent: 5317704 (1994-05-01), Izawa et al.
patent: 5335334 (1994-08-01), Takahashi et al.
patent: 5440705 (1995-08-01), Wang et al.
patent: 5649146 (1997-07-01), Riou
patent: 6157398 (2000-12-01), Teddeloh
Nizar Puthiya K.
Williams Michael W.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Nguyen Viet Q.
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