Abrading – Abrading process – With tool treating or forming
Reexamination Certificate
2000-10-19
2002-07-09
Hail, III, Joseph J. (Department: 3723)
Abrading
Abrading process
With tool treating or forming
C451S059000, C451S285000
Reexamination Certificate
active
06416401
ABSTRACT:
TECHNICAL FIELD
The present invention relates to pads having metal and/or metal compound abrasives for planarizing microelectronic substrates in mechanical and chemical-mechanical planarizing processes.
BACKGROUND OF THE INVENTION
Mechanical and chemical-mechanical planarizing processes (collectively “CMP”) are used in the manufacturing of microelectronic devices for forming a flat surface on semiconductor wafers, field emission displays and many other microelectronic-device substrates and substrate assemblies.
FIG. 1
schematically illustrates a CMP machine
10
having a platen
20
. The platen
20
supports a planarizing medium
40
that can include a polishing pad
41
having a planarizing surface
42
on which a planarizing liquid
43
is disposed. The polishing pad
41
may be a conventional polishing pad made from a continuous phase matrix material (e.g., polyurethane), or it may be a new generation fixed-abrasive polishing pad made from abrasive particles fixedly dispersed in a suspension medium. The planarizing liquid
43
may be a conventional CMP slurry with abrasive particles and chemicals that remove material from the wafer, or the planarizing liquid may be a planarizing solution without abrasive particles. In most CMP applications, conventional CMP slurries are used on conventional polishing pads, and planarizing solutions without abrasive particles are used on fixed abrasive polishing pads.
The CMP machine
10
can also include an underpad
25
attached to an upper surface
22
of the platen
20
and the lower surface of the polishing pad
41
. A drive assembly
26
rotates the platen
20
(as indicated by arrow A), and/or it reciprocates the platen
20
back and forth (as indicated by arrow B). Because the polishing pad
41
is attached to the underpad
25
, the polishing pad
41
moves with the platen
20
.
A wafer carrier
30
is positioned adjacent the polishing pad
41
and has a lower surface
32
to which a substrate assembly
12
may be attached via suction. Alternatively, the substrate assembly
12
may be attached to a resilient pad
34
positioned between the substrate assembly
12
and the lower surface
32
. The wafer carrier
30
may be a weighted, free-floating wafer carrier, or an actuator assembly
33
may be attached to the wafer carrier to impart axial and/or rotational motion (as indicated by arrows C and D, respectively).
To planarize the substrate assembly
12
with the CMP machine
10
, the wafer carrier
30
presses the substrate assembly
12
face-downward against the polishing pad
41
. While the face of the substrate assembly
12
presses against the polishing pad
41
, at least one of the platen
20
or the wafer carrier
30
moves relative to the other to move the substrate assembly
12
across the planarizing surface
42
. As the face of the substrate assembly
12
moves across the planarizing surface
42
, material is continuously removed from the face of the substrate assembly
12
.
CMP processes should consistently and accurately produce a uniformly planar surface on the substrate assembly to enable precise fabrication of circuits and photo-patterns. During the fabrication of transistors, contacts, interconnects and other features, many substrates develop large “step heights” that create a highly topographic surface across the substrate. Yet, as the density of integrated circuits increases, it is necessary to have a planar substrate surface at several stages of processing the substrate because non-uniform substrate surfaces significantly increase the difficulty of forming sub-micron features. For example, it is difficult to accurately focus photo-patterns to within tolerances approaching 0.1 &mgr;m on non-uniform substrate surfaces because sub-micron photolithographic equipment generally has a very limited depth of field. Thus, CMP processes are often used to transform a topographical substrate surface into a highly uniform, planar substrate surface.
In the competitive semiconductor industry, it is also highly desirable to have a high yield in CMP processes by producing a uniformly planar surface at a desired endpoint on a substrate assembly as quickly as possible. For example, when a conductive layer on a substrate assembly is under-planarized in the formation of contacts or interconnects, many of these components may not be electrically isolated from one another because undesirable portions of the conductive layer may remain on the substrate over a dielectric layer. Additionally, when a substrate is over-planarized, components below the desired endpoint may be damaged or completely destroyed. Thus, to provide a high yield of operable microelectronic devices, CMP processing should quickly remove material until the desired endpoint is reached.
The planarity of the finished substrate assemblies and the yield of CMP processing is a function of several factors, one of which is the rate at which material is removed from the substrate assembly (the “polishing rate”). Although it is desirable to have a high polishing rate to reduce the duration of each planarizing cycle, the polishing rate should be uniform across the substrate to produce a uniformly planar surface. The polishing rate should also be consistent to accurately endpoint CMP processing at a desired elevation in the substrate assembly. The polishing rate, therefore, should be controlled to provide accurate, reproducible results.
In manufacturing microelectronic substrate assemblies, metal features are typically incorporated into the substrate to electrically connect devices and features of the substrate. For example, metal plugs can extend between layers of the substrate assembly to connect portions of the layers, and metal interconnects can extend from one region of a layer to another to connect features on the same layer. The metal features can include a conductive element surrounded by a diffusion barrier, each formed from a different metal composition. During planarization, the material forming the conductive element typically planarizes at a faster rate than does the material forming the diffusion barrier. Accordingly, the conductive element can become “dished” relative to the surrounding diffusion barrier, resulting in an uneven surface topography. As discussed above, an uneven surface typography can make it difficult to form sub-micron devices.
One approach to addressing this problem has been to add metal oxide abrasives to the planarizing liquid
43
. For example, the planarizing liquid
43
can include titania abrasive particles to planarize a substrate assembly
12
having titania diffusion barriers or the planarizing liquid
43
can include alumina abrasive particles to planarize a substrate assembly
12
having alumina structures. However, this approach has several drawbacks as well. For example, the polishing rate can be influenced by the distribution of the planarizing liquid
43
between the substrate assembly
12
and the planarizing surface
42
of the polishing pad
41
. The distribution of the planarizing liquid
43
may not be uniform across the surface of the substrate assembly
12
because the leading edge of the substrate assembly
12
can wipe a significant portion of the planarizing liquid
43
from the polishing pad
41
before the planarizing liquid
43
can contact the other areas of the substrate assembly. The non-uniform distribution of planarizing liquid
43
under the substrate assembly
12
can cause certain areas of the substrate assembly
12
to have a higher polishing rate than other areas because they have more contact with the chemicals and/or abrasive particles in the planarizing liquid
43
. The surface of the substrate assembly
12
may accordingly not be uniformly planar, and in extreme cases, some devices may be damaged or destroyed by CMP processing.
The polishing rate may also vary from one substrate assembly to another, or even across a particular substrate, because the composition of the planarizing liquid
43
may vary. The chemicals added to the planarizing liquid
43
may degrade over time causing one batch of planarizing li
Meikle Scott
Sabde Gundu M.
Dorsey & Whitney LLP
Hail III Joseph J.
Micro)n Technology, Inc.
Ojini Anthony
LandOfFree
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