Data processing: measuring – calibrating – or testing – Measurement system – Performance or efficiency evaluation
Reexamination Certificate
2002-04-30
2004-03-16
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system
Performance or efficiency evaluation
C702S117000, C702S123000, C702S185000, C324S500000, C324S512000, C324S527000, C716S030000, C716S030000, C716S030000, C714S700000, C714S744000
Reexamination Certificate
active
06708139
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is generally related to integrated circuits (ICs) and, more particularly, to measuring the quality of delay tests used to test ICs for faults, or defects.
BACKGROUND OF THE INVENTION
After an IC is manufactured, it is tested on an IC tester before it is shipped to a customer. The goal of the testing is to verify that each individual IC was manufactured correctly without defects. At the highest level, testing may be reduced to simply plugging the IC into a host system and determining whether the system appears to be functioning normally while running applications. If the system works, then a determination may be made that the IC is ready to be shipped. However, this type of system-level test does not ensure that the IC is defect free, since the given applications used may exercise only a subset of the IC's functionality. This type of high-level system-based testing also requires a relatively large amount of time.
An alternative to the system test approach is known as functional testing. This type of testing is performed on a general-purpose IC tester (known as Automated Test Equipment, or ATE). This type of testing applies logic 1s and/or 0s to the input pins of the IC in order to stimulate all of the logic gates within the IC, and determines whether each logic gate outputs the correct result by observing the output pins of the IC. The patterns applied to and the results expected from each IC pin are stored in memory on the ATE and exercise the various functional aspects of the IC. If the IC responds correctly to all test stimuli, it is considered to be of shipment quality. However, given the complexity and sequential depth of modem ICs, creating a sufficiently thorough test to be applied via the pins is very difficult, and given the large number of pins on some ICs, the cost of the ATE resources can become prohibitive.
A third alternative to the system testing and functional testing approaches is known as structural testing. Instead of exercising the functional aspects of the IC, this type of testing applies logic 1s and/or 0s internally to stimulate all of the logic gates within the IC, and determines whether each logic gate outputs the correct result, again internally. This internal controllability and observability is obtained by using modified memory elements (flip-flops) inside the IC that are serially connected into a scan chain during test mode. This well-known technique of “scan design” has been in wide use for many years. In “full scan” designs, every internal flip-flop in the IC is made “scannable” by adding a serial access to a predecessor flip-flop and a successor flip-flop on the scan path during test mode. Thus, all the logic gates on the IC are surrounded by scannable flip-flops and become combinationally testable. In order to perform a scan test, data is serially shifted into all of the flip-flops in the scan path while the IC is in test mode, the resulting response of the logic gates to the final scanned-in state stimulus is captured by clocking all the flip-flops one or more times while the IC is in normal mode, and then by serially shifting the newly captured data out of the IC while in test mode. The captured data is analyzed by the ATE as it is shifted out to determine whether the correct results were obtained. The ATE is also responsible for switching the IC between normal and test modes appropriately as well as for providing the clock stimulus.
In order to create a structural test, a software tool uses a simulation model of the IC, which includes the scan flip-flops and all of the combinational logic of the IC. A “fault model” that represents hypothesized defects is superimposed on the simulation model of the IC in order to guide the creation of specific test patterns (also called test vectors) that are intended to expose faulty logic gates. The software tool then generates test patterns for each location in the IC model at which a fault, or defect, could exist. Each test pattern is a set of 1s and 0s that are necessary to excite and propagate the hypothesized fault to an observation point (i.e. a scannable flip-flop), as well as the expected response of a defect-free IC. If an IC responds to such a pattern with data other than that expected, then the hypothesized fault is deduced to be present and the IC is thus determined to be defective and is not shipped. The complete set of test patterns (called a test sequence or a test set) is intended to cover all possible faults in an IC.
The spectrum of all possible faults in an IC is, unfortunately, very broad. While many defects result in permanent logical errors that can be easily detected by scan-based tests, some defects manifest themselves only as increased delays in the IC. Therefore, if the scan test is performed without taking the speed at which the gates should respond into account, such “delay defects” may go undetected. For example, assuming a NOR gate that has a weak pull down transistor, the gate may produce the correct logical value if given enough time, but will not produce the value correctly under the timing specifications for the IC. Therefore, each gate must be checked to determine whether its logical function is correctly performed and whether it is performed in a timely fashion. A pattern that does not take timing into account is called a “static” test, while one that does execute under timing constraints is called a “dynamic” test. A dynamic test for a given logic gate is created by running two test patterns in sequence at full clock speed and determining whether a slow-to-rise (STR) or slow-to-fall (STF) delay fault exists.
For example, if one input of a two-input NOR gate is held at 0 for two clock cycles while the other input changes from a 0 on the first clock cycle to a 1 on the second clock cycle, the output should change from a 1 on the first clock cycle to a 0 on the second clock cycle. If the output does not change from a 1 to a 0 within specified timing margins, a slow-to-fall fault exists. Similarly, if one input of the NOR gate is held at 0 for two clock cycles while the other input changes from a 1 on the first clock cycle to a 0 on the second clock cycle, the output should change from a 0 on the first clock cycle to a 1 on the second clock cycle. If the output does not change from a 0 to a 1 within specified timing margins, a slow-to-rise fault exists.
FIG. 1
is a block diagram illustrating a series of scan flip-flops
1
,
2
, and
3
as well as combinational logic
4
of an IC that incorporates the aforementioned scan design and that can be used for performing static and dynamic tests. Each of the flip-flops
1
,
2
, and
3
has its data input, D, connected to the output of one of the multiplexers
6
,
7
, or
8
, respectively. When the scan enable signal, SC_EN is low (i.e., not asserted), the data at input 0 of the multiplexers
6
,
7
, and
8
is captured by the flip-flops
1
,
2
, and
3
, respectively, on the rising edge of the clock, CLK. Therefore, when the scan enable signal SC_EN is not asserted, the IC is functioning in the normal operational manner. The combinational logic
4
will normally receive a plurality of primary input signals
9
originating from the input pins of the IC and will drive a plurality of primary output signals
11
that terminate at the output pins of the IC. The scan chain begins at input S_I
12
and ends at output S_O
13
. The flip-flops act as a serial shift register between these two points when the scan enable signal SC_EN is asserted.
The black dots separating flip-flops
2
and
3
are intended to indicate that the scan chain may, and normally does, include many more flip-flops than the three shown in the figure (e.g., 100,000 flip-flops on a contemporary IC is not uncommon). It should be noted that corresponding additional inputs and outputs of the combinational logic
4
are connected to these additional scan flip-flops not shown in
FIG. 1
to enable every gate of the combinational logic to be tested using the scan design technique. It should also be noted that se
Rearick Jeff
Sharma Manish
Agilent Technologie,s Inc.
Desta Elias
Hoff Marc S.
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