Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
1999-03-03
2003-05-06
Broda, Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
C703S014000, C703S022000, C702S065000, C702S076000, C716S030000
Reexamination Certificate
active
06560567
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to electronic testing and characterizing of semiconductor IC processes. More specifically it relates to measurement of on-wafer capacitance in the frequency range of several MHz to about 20 GHz.
BACKGROUND ART
Integrated circuits (IC) typically contain several million electrical components (including transistors, resistors, capacitors and diodes) and its interconnections (usually metal wires). An IC's components and interconnections (collectively referred to as “conductors”) are arranged in layers. Each layer may comprise several thousand conductors. A non-conducting material or dielectric such as silicon dioxide is used to separate both the layers, and the conductors within the layers. Connections from one layer to another are made through “vias” in the dielectric so that all of the conductors may work together to perform a desired function.
A typical IC cross section comprises multiple layers. The bottom two layers, commonly referred to as the substrate and poly (short for polysilicon), are the building blocks of the IC's transistors. The layers above the poly, commonly referred to as Metal
1
, Metal
2
, and Metal
3
, comprise the wires and other conductors, called interconnects, which connect the transistors found in the lower layers.
The close spacing of the interconnects leads to a phenomenon called parasitic capacitance. Capacitance is a natural phenomenon which exists between any two conductors which are not electrically connected to each other; the closer the proximity of the conductors, the larger the capacitance. Parasitic capacitance is so named because it is an undesirable effect resulting from the very close placement of conductors in an IC. In practice, parasitic capacitance is significant between interconnects which are in close proximity to one another.
An undesirable effect of parasitic capacitance is to slow the propagation of electrical signals through a circuit, thereby reducing the speed at which an IC can function. The larger the parasitic capacitance, the greater the delay a signal will encounter as it travels through a conductor. If the parasitic capacitance components of an IC can be extracted from the IC's physical design, they can be used to estimate the delay for each signal in the circuit, a process known as timing analysis. This information may be used to adjust the physical layout of conductors in an IC, thereby optimizing the performance of the IC's circuits.
FIG. 14
shows the most basic method of measuring capacitance. The precision LCR (Inductance, Capacitance and Resistance) meter
1402
is directly connected to the device under test (DUT)
1404
. Inside the LCR meter is a circuit that has an effective reactance, such as an inductance that is compared to the reactance of the DUT at a specific frequency, such as a few hundred KHz. Then the reactance at the known frequency is translated into an effective capacitance value. Other techniques are known.
In U.S. Pat. No. 4,992,740, Wakasugi et al. use a “simulated inductor” in order to measure the capacitance of the DUT. In this patent, an active circuit is used to create an “artificial inductor” which is then used to measure the DUT, which may be a resistor, a capacitor, or an inductor. The focus of the '740 patent is to substitute a very large “artificial inductance” made from an active circuit in place of a real passive inductor in order to provide the required inductance at low frequencies.
In U.S. Pat. No. 5,790,479, Conn et al. use a reference ring oscillator to measure the capacitance of the interconnect. Ring oscillators are usually used to characterize the transistors that make up the ring oscillator. In the '479 patent, an additional loaded ring oscillator is compared to an unloaded ring oscillator to determine the load, which is the capacitance of the DUT. The ring oscillator is an active circuit made from inverting logic gates, each having a gain greater than 1. However, the use of active devices increases uncertainty in the value of the load, because (a) by virtue of operating in the active mode, the devices have appreciable capacitance which cannot be ignored and more significantly cannot be easily predicted and (b) the presence of the periodically placed load is likely to cause an unpredictable change in the geometry of the devices of the loaded ring. For example, the '479 patent makes a fundamental assumption that there is no difference between the active devices comprising the loaded ring oscillator as compared to the unloaded ring oscillator, an assumption that cannot realistically be made.
In U.S. Pat. No. 5,793,640, Wu et al. use two measurements of the reactance of the DUT by an HP4275 LCR meter to model the DUT as an RLC equivalent circuit, or alternatively as a parallel RC circuit as opposed to a series RC equivalent circuit as is done inside the HP4275 LCR meter and extract the capacitance C from the real and imaginary components at the two frequencies. Briefly, in this patent the authors make the point that internal to the HP4275 LCR meter first the effective impedance of the DUT is measured and internally the capacitance is extracted from the effective impedance by modeling the DUT as a series RC circuit. The authors state that the results are better if the DUT is modeled as a parallel RC circuit instead of as a series RC circuit. The DUT is still measured as recommended by Hewlett-Packard in the HP4275 LCR measurement manual.
In U.S. Pat. No. 5,831,870 Folta et al. outline a method for estimating the parasitic capacitances in a VLSI circuit starting from the layout of the circuit. Unlike the previous patents, this is not a measurement technique, and is actually a description of an algorithm to be used in a parasitic extractor software used to estimate parasitic capacitances in commercial circuits based on constants that were previously estimated by techniques such as are described in the '740, '479 and '640 patents. It relates to a method and system for data processing in general and, in particular to a method and system for characterizing data for capacitance estimation.
In U.S. Pat. No. 5,838,582 which is related to the previous patent, also by IBM, Mehrotra et al. detail another algorithm for efficient data processing to estimate capacitances in a VLSI circuit based on constants that were previously estimated by techniques such as are described in the '740, '479 and '640 patents.
In a publication entitled “High-Speed VLSI Interconnect Modeling Based on S-Parameter Measurements”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology (Vol. 16, No. 5, August 1993), Eo et al. detail a technique that involves S-parameter measurements. Here the DUT is a two port circuit. However, it is not a filter comprised of many elements, but is a simple transmission line. For this reason, this technique is unsuitable for measuring lumped capacitances such as the gate capacitance of a transistor or an interdigitated interconnect capacitor.
In another publication, entitled “An On-Chip, Attofarad Interconnect Charge-Based Capacitance Measurement (CBCM) Technique”, SRC Pub C96581 (December 1996), Chen et al. measure the DC current utilization of two identical switching circuits, one with and one without the DUT capacitance as the load of an inverter circuit. The difference is used to compute the capacitance of the DUT. The problem with this technique is the requirement that the transistors match exactly, a condition which realistically is not attainable. It is also a critical requirement that the equipment used to measure the currents in both branches match each other exactly, which is also never the case.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of accurately measuring complex impedances, such as small lumped capacitances, of devices fabricated on-wafer and over a range of frequencies from 50 MHz to 20 GHz. The method in accordance with the invention includes selecting a device under test (DUT)
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