Method and apparatus for measuring EEPROM threshold voltages in

Details Method and apparatus for measuring EEPROM threshold voltages in Method and apparatus for measuring EEPROM threshold voltages in

1990-09-20

1992-10-06

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365203, 365201, G11C 700

Patent

active

051538539

ABSTRACT:
A method and apparatus for measuring threshold voltages associated with the EEPROM portion of a non-volatile DRAM (NVDRAM) memory cell. The DRAM node of the NVDRUM cell is charged to a high potential and allowed to discharge through the EEPROM transistor. Since the gate of the EEPROM is tied to the DRAM node, the DRAM node voltage, which is also the EEPROM gate-to-source voltage, will, if the NVDRAM is left alone, drop until the EEPROM transistor shuts off. The EEPROM gate-to-source voltage at any point in time along this discharge path is measured through an iterative process. First, timing signals are adjusted to specify the point in time at which the EEPROM voltage is to be measured. Then, during each iteration, the EEPROM voltage is charged up and allowed to the discharge. At the point in time along the discharge path specified by the timing signals, a reference voltage is compared with the EEPROM voltage to determine if the reference voltage is above or below the EEPROM voltage. Over several such iterations, the reference voltage is adjusted closer and closer to the EEPROM voltage. The value of the reference voltage at the point where it crosses the EEPROM voltage is an approximation of the EEPROM voltage at the specified measuring time.

REFERENCES:
patent: 4611309 (1986-09-01), Chuang et al.

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