Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation
Reexamination Certificate
1999-01-21
2002-11-26
Wachsman, Hal (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Quality evaluation
C702S035000, C702S081000, C702S118000, C700S110000, C700S109000, C700S121000
Reexamination Certificate
active
06487511
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to improving the yield and processing of semiconductor devices, and, more particularly, to measurement of cumulative defect analysis in semiconductor processes.
2. Description of the Related Art
The proliferation of the high technology industry has resulted in many innovations that improve our ability to create useful electronic devices. One commodity that is at a premium in the high technology industry is the semiconductor device. Semiconductor devices have become integral components in high technology products. The demands placed upon the high technology sector has created the need for new and creative solutions for issues regarding semiconductor designing, testing, and manufacturing. Many of these design, test, and manufacturing issues are not readily contemplated by many in the field. One such issue arises when defect data is collected during processing of semiconductor wafers.
The manufacture of integrated circuits (IC) is a complex and lengthy process involving hundreds of steps and rigorous manufacturing control. A variety of films, both conductive and insulative, are applied in successive steps to a semiconductor substrate (wafer). Each semiconductor wafer is subdivided into individual units, called die, and identical patterns are printed onto each die. The smallest features of these patterns extend into the sub-micron regime, hundreds of times smaller than a human hair.
During fabrication, several hundred potentially usable die are formed on the surface of a wafer. However, for a variety of reasons, such as manufacturing errors, not all of the die will result in a useful semiconductor product. Yield is a term used by the semiconductor industry to indicate the amount of usable die divided by the number of possible good die. Yield is typically expressed as a percentage since manufacturing processes are not perfect. Yield is of paramount importance to the IC manufacturer; companies stand to lose millions of dollars in profits if wafers do not yield according to projections. Defects introduced during the manufacturing process may cause die to fail, driving yield down. Thus, it is very important to monitor the yield of various manufacturing processes used to make semiconductor devices.
Defects can be generated by process tools, humans, or the environment in the manufacturing facility (the fab). Small particles, scratches, and residues from process tools are some of the types of defects that can corrupt a die. IC manufacturers utilize multi-million dollar tools to inspect wafer surfaces at critical points in the process in order to monitor the viability of the product. Some of these inspection tools generally use digital image comparison or laser scattering methodologies to “scan” the wafers and determine the presence of defects. The defect information (number, location on the wafer, size, etc.) for each wafer is then typically fed into a large database for further analysis. Technicians on the factory floor review the defects located by the scan tools using sophisticated microscopes and classify the defects (e.g., embedded particle, surface flake, pattern defect, etc.); these classifications are also fed into the database.
There are many types of defect analysis, yet no true industry-wide standard techniques exist. The current state-of-the-art relating to defect analysis leaves much room for improvement. Quite often, wafers reach the end of a process line and yield poorly. Vast amounts of resources are then fielded to investigate and determine the cause or causes of poor yield.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for determining a cumulative defect measure for a wafer lot. A wafer lot is selected for inspection. At least one wafer from the lot for inspection is selected. The wafer comprises a plurality of process layers and at least some of the process layers are selected for inspection for defects. The number, type, and kill ratio of the defects on each layer of the wafer are determined. A cumulative defect measurement for the wafer is determined based upon the number, type, and kill ratio of the defects on all inspected layers on the wafer. The cumulative defect measurement for the wafer is extrapolated to determine a quantified indication of a defectiveness of the selected wafer lot.
The present invention further provides for an apparatus for determining a cumulative defect measure for a wafer lot, comprising a wafer processing line. A process control system interfaces with the wafer processing line and is capable of controlling the wafer processing line. A communication system, interfacing with the process control system, is capable of sending and receiving data. A system control is coupled to the communication system, and is capable of controlling the process control system. The apparatus of the present invention further comprises a means for calculating a cumulative defect measure for a wafer lot.
REFERENCES:
patent: 5773315 (1998-06-01), Jarvis
patent: 5777901 (1998-07-01), Berezin et al.
patent: 5917332 (1999-06-01), Chen et al.
patent: 5991699 (1999-11-01), Kulkarni et al.
patent: 6098024 (2000-08-01), Chen et al.
patent: 6185707 (2001-02-01), Smith et al.
patent: 6246787 (2001-06-01), Hennessey et al.
Advanced Micro Devices , Inc.
Wachsman Hal
Williams Morgan & Amerson P.C.
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