Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
2001-12-27
2004-02-10
Chang, Kent (Department: 2673)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
C348S581000, C345S698000
Reexamination Certificate
active
06690368
ABSTRACT:
This application incorporates by reference of Taiwan application Serial No. 090100317, filed on Jan. 5, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method for measuring a full frame size from a display signal and an apparatus therefor, and more particularly to a method for measuring a fill frame size from a display signal by a data enable signal and an apparatus therefor.
2. Description of the Related Art
For maintaining the display quality, a display monitor, such as a cathode ray tube (CRT) or liquid crystal display (LCD) monitor, is required to adjust the size and position of the full frame indicated by a display signal applied to the display monitor. In order to display frames indicated by the display signal in a proper position on the screen of the display monitor, the display monitor requires determining the display parameters such as a full frame size. For illustrating the problem behind a conventional approach, the following description will explain the circuitry of the display monitor, the display signal, and the determination of the full frame size and position.
The circuitry for a display monitor is illustrated in FIG.
1
. The display monitor includes a differential signal receiving/decoding device
110
and a ratio processing device. A display signal applied to a display monitor is generally a low voltage differential (LVD) encoded signal. The LVD encoded signal is indicative of signals including three primary color signals, a horizontal synchronous signal Hs, a vertical synchronous signal Vs, a data enable signal DE, and a pixel clock CK. In
FIG. 1
, the LVD encoded signal
102
includes signals denoted by Rx
0
−, Rx
0
+, Rx
1
−, Rx
1
+, Rx
2
−, Rx
2
+, RxC−, and RxC+. Since the display monitor can only display digital signals, before processing these signals, the display monitor employs a differential signal receiving/decoding device
110
to convert and decode these signals into a digital display signal
104
. On receiving the LVD encoded signal
102
, the differential signal receiving/decoding device
110
converts and decodes the LVD encoded signal
102
into the digital display signal
104
(i.e., three primary color signals including red (RD), green (GD) and blue (BD) signals), the horizontal synchronous signal Hs, the vertical synchronous signal Vs, the data enable signal DE, the pixel clock signal CK, and so on. When the digital display signal
104
is applied to a ratio processing device
130
, an optimal output video signal can be obtained by phase adjustment or interpolation provided by the ratio processing device
130
. Since the phase adjustment or interpolation is not the key to the measurement of the full frame size, they will not be described for the sake of brevity. The operation of the display monitor with the horizontal synchronous signal Hs, the vertical synchronous signal Vs, the data enable signal DE, the pixel clock signal CK will be described in the following.
The horizontal synchronous signal Hs, the vertical synchronous signal Vs, the data enable signal DE, and the pixel clock signal CK have units of frequency. The pixel clock signal CK indicates number of pixels to be displayed per second and determines intervals between a pixel to display color and the next one to display color. Upon receiving data of a frame, the display monitor displays colors of pixels of the frame line by line. First, the first pixel of the first line displays color. Second, the second pixel of the first line displays color. The process proceeds in the similar manner until the last pixel of the first line display colors. Next, the next line, such as the second line, display colors in the same manner from the first pixel to the last pixel. Likewise, the process proceeds until the last pixel of the last line displays color. Due to persistence of vision provided by human vision system, all of the pixels on the screen form the required frame. On receiving another frame, the display monitor displays the frame according to the same manner. It should be noted that, after the last pixel of each of the lines displays color, the horizontal synchronous signal Hs causes the scanning of pixels for displaying color to proceed from the first pixel of the next line. Thus, the horizontal synchronous signal Hs determines the number of rows of pixels to be display color per second. In addition, after the pixel of the last column and last row displays color, the vertical synchronous signal causes the scanning of pixels for displaying color to proceed from the pixel at the first column and first row. Thus, the vertical synchronous signal determines the number of frames to be displayed per second. Since human vision system provides persistence of vision, the frames displayed at a rate faster than a threshold value will become continuous movement of objects, i.e., a movie picture. The rate that the display monitor refreshes different frames on the screen is called a refresh rate, i.e., the frequency of the vertical synchronous signal Vs. The refresh rate for generally computer display systems is 60 Hz or above; i.e., the display monitor displays at least 60 frames per second. In the following, the timing relationship of the horizontal synchronous signal Hs, the vertical synchronous signal Vs, the data enable signal DE, and the pixel clock signal CK will be explained.
FIG. 2
illustrates the timing relationship of the horizontal synchronous signal Hs, the vertical synchronous signal Vs, and the data enable signal DE. Take the resolution of 1024×768 pixels as an example. For this resolution, the horizontal synchronous signal Hs, the vertical synchronous signal Vs, and the pixel clock signal CK can be 48.36 kHz, 60 Hz, and 65 MHz respectively. During displaying frames, 60 frames are displayed for every second and the Vs signal changes its state only after 768 cycles of the Hs signal because there are 768 rows per frame. In addition, the data enable signal DE determines the period of the display of each row. For each row, 1024 pixels are required to be displayed. Thus, when the enable signal DE is asserted, the display monitor displays colors of 1024 pixels. Having a fixed frequency, the pixel clock signal CK correspondingly oscillates for 1024 cycles during the assertion of the data enable signal DE, as shown in FIG.
2
B. The color information of the 1024 pixels is then obtained by sampling the digital display signal through the pixel clock signal CK and the sampled color information is applied to the 1024 pixels during the assertion of the data enable signal DE. Thus, the data enable signal DE can be used to determine the width of the full frame size.
FIG. 3
further illustrates how a display area relates to the above-mentioned signals. A display area
300
shown in
FIG. 3
indicates an array of 1024×768 pixels. Since the color of each pixel in the display area
300
is displayed by sampling the digital display signal through the pixel clock signal CK, all of the pixels of each row correspond to 1024 pulses of the pulse train of the pixel clock signal CK. As shown in
FIG. 3
, the length of each row on the display area
300
is determined by the data enable signal DE when the data enable signal DE is asserted. Although the horizontal synchronous signal Hs determines the display of each row on the display area
300
, the length of the each row is not determined by the Hs signal. Besides, after the beginning and before the ending of every time interval during which the Hs signal is asserted, there are time intervals during which the Hs signal does not correspond to the display area
300
(i.e., time intervals during which the Hs signal correspond to areas outside the display area
300
and without pixels to be displayed), wherein the time intervals are commonly referred to as a back porch and a front porch respectively. For example, on the left side of the display area
300
, a rectangle with dotted borders corresponds to a back porch BPH of the Hs signal. On the right side of th
Benq Corporation
Chang Kent
Rabin & Berdo P.C.
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