Computer graphics processing and selective visual display system – Computer graphics processing – Three-dimension
Reexamination Certificate
1998-08-12
2001-04-10
Vo, Cliff N. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphics processing
Three-dimension
C345S519000
Reexamination Certificate
active
06215497
ABSTRACT:
FIELD OF THE INVENTION
The present invention is applicable in the field of digital data processing in which a dynamic random access memory (DRAM) is employed for storing digital information. In general, the present invention is used in an integrated circuit in which DRAM is embedded to provide data storage to support on-chip as well as off-chip data processing. The invention also relates to the application of embedded DRAM in the field of computer graphics.
DESCRIPTION OF RELATED ART
Conventional computer systems have used embedded DRAM in different manners. Embedded DRAM is defined as a DRAM that is physically embedded on a chip that includes a larger system, and whose purpose is to provide a memory function for the other components of the system in order to achieve the overall system objectives.
U.S. Pat. No. 5,249,282 by Segers describes a system that uses embedded DRAM as a cache memory. In this system, the embedded DRAM serves as a secondary cache to an on-chip central processing unit (CPU). However, because the embedded DRAM is logically configured as a single large array, the average DRAM cache access time is relatively long.
Another embedded DRAM system is described in an article entitled “NeoMagic Puts Graphics System in One Chip”, Microprocessor Report, March 1995. This article describes a 1 Mbyte DRAM that is embedded in a chip with a 2-D graphics processor. The embedded DRAM serves as a display frame storage, and implements off-screen temporary storage. However, the embedded DRAM is a single large array, thereby causing the average DRAM access time to be relatively long.
As described above, embedded DRAM of conventional systems suffer the same relatively long access and memory cycle time as stand alone DRAM. The long access and memory cycle time results in low average bandwidth as the data bus is idle during most accesses while waiting for the memory data. One way to recover some of the lost bandwidth to idle is to take advantage of the spatial locality of the references of most accesses by using burst accesses (as exemplified by SDRAM or SGRAM). However, in an embedded DRAM environment, the on-chip data bus is typically very wide. As a result, the data associated with a conventional sequential burst access can typically be accessed in a single clock cycle in embedded DRAM, thereby making burst access of an embedded DRAM an unlikely event. This is especially true for graphics applications where multiple processing units with different spatial locality of references access the embedded DRAM simultaneously.
A DRAM using a multi-bank architecture to reduce the average access time is described in “A 32-bank 256-MB DRAM with Cache and TAG” by S. Tanoi et al., IEEE JSSC, vol. 29, No. 11, November 1994, pp. 1330-1335. In this scheme, the sense-amplifiers of some of the banks are used as cache memory to speed up the access at the expense of longer access time on cache miss access. The access control in the memory is also complicated by the addition of a TAG memory and a cache control circuit in each bank.
Another embedded DRAM is described in the article, “An Access-Sequence Control Scheme to Enhance Random-Access Performance of Embedded DRAM's”, by K. Ayukawa et al., IEEE JSSC, vol. 33. No. 5, May 1998, pp. 800-806”. This article proposes the use of multiple banks to reduce the average access time of the embedded DRAM. In this system, the embedded DRAM is accessed using a relatively complicated access control scheme that includes the use of a separate, dedicated data ID bus. This data ID bus is used to allow out-of-order accesses, thereby shortening the average DRAM access time. A memory is said to be able to handle out-of-order accesses if a second access transaction begins later than a first access transaction, and finishes before of the first access transaction. A write buffer having a depth of four entries is used to shorten the write access. However, the memory cycle time of the embedded DRAM is 7 clock periods, and there is no provision for handling the case where there are four or more consecutive page-miss write accesses when the write buffer is overrun.
Therefore it is desirable to have an embedded DRAM which can support random accesses at a rate that approaches one access per clock cycle (like an SRAM), without incurring the burden of having to handle out-of-order accesses. Such an embedded DRAM would be particularly useful in graphics applications.
SUMMARY
Accordingly the present invention provides a graphics sub-system having a 2-D graphics accelerator, a 3-D graphics accelerator and an embedded DRAM memory. The embedded DRAM memory serves as a frame buffer memory and/or a temporary storage memory for the 2-D graphics accelerator. The embedded DRAM memory also serves as a cache memory for the 3-D graphics accelerator.
The embedded DRAM memory is logically divided into a plurality of independent banks, thereby allowing parallel operations in multiple banks, and resulting in a relatively fast average memory cycle time. More specifically, the embedded DRAM memory processes one transaction per clock cycle for accesses with no bank conflicts. The maximum memory access time for any transaction (e.g., a bank-conflict access) is equal to memory cycle time plus the memory access time minus 1 clock cycle.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 5249282 (1993-09-01), Segers
patent: 5949439 (1999-09-01), Ben-Yoseph et al.
patent: 6023745 (2000-02-01), Lu
patent: 6026478 (2000-02-01), Dowling
patent: 6032225 (2000-02-01), Shiell et al.
Bever Hoffman & Harms LLP
Hoffman E. Eric
Monolithic System Technology, Inc.
Vo Cliff N.
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