Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-12-28
2003-02-04
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185110
Reexamination Certificate
active
06515906
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of non-volatile memories. More specifically, the present invention relates to an apparatus, method, and system for an improved sensing architecture for non-volatile memories.
BACKGROUND OF THE INVENTION
Metal-oxide-semiconductor (“MOS”) flash memory devices typically use memory cells having electrically isolated gates, called floating gates. A cross-sectional view of a typical floating gate flash EEPROM cell
100
is shown in FIG.
1
. In
FIG. 1
, the flash memory cell
100
is formed on a silicon substrate such as the p-type substrate
115
. The flash cell
100
includes a pair of spaced-apart doped regions
112
and
113
disposed in substrate
115
. Region
113
comprises a source and region
112
comprises a drain. The source
113
and the drain
112
define an active silicon region
104
and a channel between the source
113
and the drain
112
. A polysilicon floating gate
110
is disposed above and between the drain
112
and source
113
and insulated therefrom by a thin layer of silicon dioxide or other electrically insulative layer
114
. The floating gate
110
is insulated from a second control gate
111
disposed above floating gate
110
and insulated therefrom by an interpoly dielectric layer
109
. Interpoly dielectric layer
109
may be variously formed of a single layer of silicon dioxide, or of an oxide/silicon nitride/oxide multilayer dielectric of appropriate thickness. The control gate
111
is fabricated from a second layer of polysilicon deposited subsequent to the interpoly dielectric layer
109
.
A typical flash memory device typically has a memory array that is arranged into a number of blocks. Each block contains a plurality of memory cells organized into rows and columns as shown in FIG.
2
. Memory cells are placed at intersections of word lines and bit lines. Each word line is connected to the gates of the memory cells in one row. Each bit line is connected to the drains of the memory cells in one column. The sources of all memory cells are connected to a common source line. In this configuration, the word lines and bit lines of a particular block only extend within that particular block. The memory array configuration shown in
FIG. 2
also includes a number of global bit lines that are extended through a plurality of blocks. Each local bit line within a block can be individually selected to connect to (or deselected to disconnect from) a corresponding global bit line via a select transistor based upon corresponding local select signal. Each global bit line can be individually selected or deselected via a corresponding select transistor based upon a corresponding global select signal.
Typically, to sense data stored in the memory cells of the memory array of a flash memory device, an array of reference cells (called reference cell array) is used to compare against the data stored in the memory cells. The reference cell array typically contains flash cells trimmed to a known state. As such, the state of a particular memory cell can be compared with the known state of a corresponding reference cell using a sense amplifier to determine the state of data stored in that particular memory cell.
FIG. 3
shows a block diagram of a typical flash memory architecture that contains a reference cell array
370
used for sensing data stored in a memory array
310
. As shown in
FIG. 3
, the memory array
310
is organized into a plurality of blocks (
310
-
0
through
310
-N) each of which contains a plurality of memory cells. To perform a read operation with respect to one or more memory cells in a particular block, the respective memory cells can be individually selected by the corresponding word line(s), local bit line(s) (not shown) and global bit line(s). For example, to read data stored in a particular memory cell, the drain of that particular memory cell is coupled to a corresponding global bit line which is coupled to a corresponding sense amplifier. The drain of corresponding reference cell in the reference cell array is also coupled to the sense amplifier. The current from the selected memory cell is then compared against the current from the corresponding reference cell to determine the state of data stored in the selected memory cell. A problem with this architecture is that the global bit line that is used to connect the selected memory cell to the sense amplifier is much longer than the line used to connect the reference cell to the sense amplifier. As a result, the coupling capacitance and hence the coupling noise associated with the global bit line is much greater than that associated with the line connecting the reference cell to the sense amplifier. Therefore, the difference between the length of the global bit line and that of the reference line can negatively affect the accuracy of the reading of the selected memory cell. This problem may be much more severe with respect to multi-level cells which are used to store multiple bits of data per memory cell by charging the polysilicon floating gate of a memory cell to different levels. Reading of multi-level cells therefore requires a much higher level of sensing accuracy and lower tolerance for any difference in coupling capacitance and coupling noise between the line that connects the memory cell to the sense amplifier and the line that connects the reference cell to the sense amplifier.
Accordingly, there exists a need for an improved sensing architecture in flash memory devices that will enhance the accuracy of data reading/sensing.
REFERENCES:
patent: 5969979 (1999-10-01), Hirano
patent: 5999439 (1999-12-01), Seyyedy
patent: 6028783 (2000-02-01), Allen et al.
patent: 6111777 (2000-08-01), Ogiwara et al.
Jungroth Owen W.
Srinivasan Balaji
Tedrow Kerry D.
Blakely , Sokoloff, Taylor & Zafman LLP
Ho Hoai
Intel Corporation
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