Patent
1994-08-26
1997-03-04
Lane, Jack A.
3954211, G06F 1200
Patent
active
056088884
ABSTRACT:
A 2-dimensional display space is mapped into the external DRAM addresses by embedding in the address space X and Y vectors of the display space. The mapping of the X and Y vectors allows a macroblock of pixels to be stored in one DRAM memory page, so that an access to a macroblock can be efficiently accomplished under a page mode access to the DRAM page. By providing control to one address bit, data of four pixels can be obtained at one time in one of 2 pixel.times.2 pixel "quad pixel" configuration, or in a 4 pixel.times.1 pixel horizontal "scan" configuration. In addition, a structure and a method are provided for accessing a 16.times.16-pixel picture area in two parts, in order that the number of DRAM page boundaries crossed during access of the 16.times.16-pixel picture area is minimized, thereby increasing the efficiency of memory access by reducing the overhead cost of initial accesses under page mode access to DRAMs.
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Galbi David E.
Liao Frank H.
Purcell Stephen C.
Tse Yvonne C.
C-Cube Microsystems Inc.
Kwok Edward C.
Lane Jack A.
Verbrugge Kevin
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