Method and apparatus for mapping a linear address to a tiled add

Details Method and apparatus for mapping a linear address to a tiled add Method and apparatus for mapping a linear address to a tiled add

1998-04-10

2000-06-06

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Integrated circuit

711203, G06F 1206

Patent

active

060725079

ABSTRACT:
A method and apparatus for mapping a linear address to a tiled address that reduces latency between retrieval of pages of data is accomplished when a video graphics processor receives a linear address from the central processing unit and determines whether the linear address is referencing a tiled surface, which is one of up to four portions of the memory. If so, the video graphics processor obtains parameters of the tiled surface. Having obtained the parameters, the video graphics processor determines a normalized linear address based on at least one of the parameters and the linear address. Having done this, the video graphics processor determines a band pointer of the tiled surface based on at least one of the parameters, the normalized linear address and a modular function. In essence, the band pointer points to a normalized initial address of a band of a tiled surface, which includes a plurality of bands. Having obtained the band pointer, the video graphics processor then determines a linear band offset based on the band pointer and at least one of the parameters. Next, a tiled band offset is determined based on the linear band offset. Finally, the tiled address is determined based on the tiled band offset, the band pointer, and at least one of the parameters.

REFERENCES:
patent: 5828382 (1998-10-01), Wilde
patent: 5844576 (1998-12-01), Wilde et al.
patent: 5990912 (1999-11-01), Swanson

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