Semiconductor device manufacturing: process – Including control responsive to sensed condition
Reexamination Certificate
2005-12-27
2005-12-27
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Including control responsive to sensed condition
C438S006000, C438S007000, C438S008000, C438S009000, C438S313000, C430S030000
Reexamination Certificate
active
06979577
ABSTRACT:
Concerning a plurality of wafers which compose one lot, amounts of misalignment between alignment marks of these wafers and alignment patterns transferred on photoresists are measured in advance, and then, a mutual relation between a thickness of an interlayer dielectric film and a value of Wafer Scaling is calculated. When exposure is actually executed, first, an interlayer dielectric film is formed on the alignment marks in a lot and planarized. After that, the thickness of the interlayer dielectric film after planarization is measured. The value of the Wafer Scaling is estimated from an average value of the thicknesses of the interlayer dielectric films in the lot and the above-mentioned mutual relation. Then, photoresists are coated on the interlayer dielectric films in the lot, and the photoresists are exposed while the correction is executed so as to compensate the value of the Wafer Scaling.
REFERENCES:
patent: 6537835 (2003-03-01), Adachi et al.
patent: 2004/0002171 (2004-01-01), Gotkis et al.
patent: 7-167614 (1995-07-01), None
FASL LLC
Fourson George
Maldonado Julio J.
Westerman Hattori Daniels & Adrian LLP
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