Cleaning and liquid contact with solids – Apparatus – With movable means to cause fluid motion
Reexamination Certificate
1996-12-23
2001-03-13
Stinson, Frankie L. (Department: 1746)
Cleaning and liquid contact with solids
Apparatus
With movable means to cause fluid motion
C134S902000
Reexamination Certificate
active
06199567
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor device, and more particularly relates to a method of manufacturing a semiconductor device provided with a capacitor. The invention further relates to a method of manufacturing a semiconductor device provided with an interconnection pattern. The present invention still further relates to an apparatus for manufacturing such semiconductor devices.
2. Description of the Background Art
Dynamic Random Access Memories (hereinafter referred to as DRAM) can be classified into several types according to the capacitor structure. One example of the capacitor, a stacked type capacitor, can easily secure a sufficient capacitance even if device elements are miniaturized as a semiconductor device has been highly integrated, since the structure of the stacked type capacitor increases opposing areas of capacitor electrodes. Accordingly, the stacked type capacitor has been widely utilized with higher integration of a semiconductor device.
FIG. 12
is a cross sectional view of a DRAM provided with a conventional stacked type capacitor (hereinafter referred to as first conventional example). With reference to
FIG. 12
, an isolation oxide film
333
for electrically isolating element regions from each other is formed at a surface of a silicon substrate
331
. Under isolation oxide film
333
, a channel stopper region
335
is provided. A memory cell of a DRAM is formed at an element region of silicon substrate
331
. The memory cell includes one transfer gate transistor
330
and one capacitor
320
.
An interlayer insulating film
301
is formed over the entire surface of silicon substrate
331
to cover capacitor
320
. A contact hole
301
a
is provided in interlayer insulating film
301
for exposing a surface of one source/drain region
325
. At the one source/drain region
325
, a bit line
337
is formed through contact hole
301
a.
Bit line
337
is formed of a polycrystalline silicon
337
a
and a tungsten silicide layer
337
b.
An insulating film
319
is formed over silicon substrate
331
to cover bit line
337
.
A problem in the semiconductor memory device shown in
FIG. 12
is that patterning in the lithography step is difficult due to a level difference.
A semiconductor memory device illustrated in
FIG. 13
is thus proposed in order to solve such a problem.
Referring to
FIG. 13
, an isolation oxide film
33
is provided at a surface of a silicon substrate
31
. A channel stopper region
35
is formed contacting with the lower surface of isolation oxide film
33
. A plurality of transfer gate transistors
30
are formed at an element region of silicon substrate
31
.
Transfer gate transistor
30
includes a gate oxide film
21
, a gate electrode
23
, and a pair of source/drain regions
25
. An insulating film
27
is formed over silicon substrate
31
to cover a surface of gate electrode
23
.
A bit line
37
is connected to one source/drain region
25
. An interlayer insulating film
41
is provided over silicon substrate
31
to cover bit line
37
and transfer gate transistors
30
.
A contact hole
41
a
is formed in interlayer insulating film
41
for exposing the other source/drain region
25
. A plug layer
43
a
formed of doped polysilicon, filling contact hole
41
a
and connected to the other source/drain region
25
, is provided on silicon substrate
31
. A barrier layer
13
has a triple layer structure including titanium/titanium nitride/titanium. A capacitor
10
is connected to plug layer
43
a
with barrier layer
13
interposed.
Capacitor
10
is provided with a lower electrode layer
1
, a capacitor insulating layer
3
and an upper electrode layer
5
.
Barrier layer
13
prevents diffusion of impurities from plug layer
43
a
formed of doped polysilicon toward lower electrode layer
1
, and improves adhesion between interlayer insulating film
41
and lower electrode layer
1
.
Lower electrode layer
1
is deposited on a surface of interlayer insulating film
41
to a film thickness of 500 to 700 Å with barrier layer
13
interposed. Lower electrode layer
1
is formed of platinum. On a surface of lower electrode layer
1
, capacitor insulating layer
3
formed of highly dielectric material such as tantalum oxide (Ta
2
O
5
), plumbous-zirconate-titanate (PZT), plumbous-lanthanum-zirconate-titanate (PLZT), strontium titanic oxide (STO), or barium titanic oxide (BTO) is formed.
PZT and PLZT have the maximum relative dielectric constant when formed on platinum. Therefore, lower electrode layer
1
is preferably formed of platinum.
A sidewall spacer
11
a
is formed on interlayer insulating film
41
to cover sidewalls of lower electrode layer
1
and capacitor insulating layer
3
. Sidewall spacer
11
a
provides dielectric isolation between lower electrode
1
and upper electrode
5
described below. Upper electrode layer
5
is formed to cover lower electrode layer
1
with capacitor insulating layer
3
and sidewall spacer
11
a
interposed, thus providing capacitor
10
. Upper electrode layer
5
is formed of platinum, doped polysilicon or the like. An insulating film
45
is formed over silicon substrate
31
to cover capacitor
10
.
Although the semiconductor device shown in
FIG. 13
does not have the problem found in the first conventional example, it has another problem.
The problem will be pointed out in the description of the manufacturing method of the semiconductor device (
FIGS. 14
to
23
).
Referring to
FIG. 14
, transfer gate transistor
30
having gate oxide film
21
, gate electrode
23
and a pair of source/drain regions
25
is provided on silicon substrate
31
. Insulating film
27
covers an outer surface of gate electrode
23
. Bit line
37
connected to one source/drain region
25
is formed over silicon substrate
31
. Bit line
37
is formed, for example, of doped polysilicon.
A silicon oxide film to be interlayer insulating film
41
is formed by low pressure CVD (Chemical Vapor Deposition) over silicon substrate
31
to cover bit line
37
and transfer gate transistor
30
. SOG film (not shown) is applied to a surface of the silicon oxide film in order to planarize the surface. Interlayer insulating film
41
having almost planar surface is provided by etching back the SOG film and the silicon oxide film.
With reference to
FIG. 15
, a resist pattern
51
having an aperture
51
a
over one source/drain region
25
is formed on interlayer insulating film
41
. Interlayer insulating film
41
is anisotropically etched using resist pattern
51
as a mask. Contact hole
41
a
for exposing the surface of one source/drain region
25
is formed in interlayer insulating film
41
through etching. Resist pattern
51
is thereafter removed.
Referring to
FIG. 16
, a doped polysilicon film
43
filling contact hole
41
a
and contacting one source/drain region
25
is formed over silicon substrate
31
. Doped polysilicon film
43
is formed by CVD method to a film thickness of 3000 to 9000 Å.
With reference to
FIGS. 16 and 17
, doped polysilicon film
43
is etched back until at least the surface of interlayer insulating film
41
is exposed. Plug layer
43
a
filling contact hole
41
a
and electrically connected to the surface of one source/drain region
25
is provided through this etch back.
Referring to
FIG. 18
, barrier layer
13
in contact with the surface of plug layer
43
a
is formed on the surface of interlayer insulating film
41
. Barrier layer
13
is formed of triple layers of titanium, titanium nitride and titanium, and each layer is generated one after the other by sputtering method to the thickness of approximately 100 Å. In order to cause reaction between the lowest titanium layer with interlayer insulating film
41
and produce silicide, they are thermally processed in an ambient of nitrogen or argon with a temperature of 650° C. for 20 minutes. A platinum layer
1
is deposited to a film thickness of 500 to 700 Å on barrier layer
13
by CVD. In order to alloy t
Aoyama Tetsuo
Hada Mayumi
Kanno Itaru
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Stinson Frankie L.
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