Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1996-11-12
1999-03-02
Talbot, Brian K.
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
427 97, 4273881, 427409, 264138, 264139, 264104, 264255, B05D 512, B28B 722
Patent
active
058767894
ABSTRACT:
In a first step, a conductive layer a1 is formed on a three-dimensionally curved upper surface of a main mold. In a second step, a peripheral surface mold is attached to the outer peripheral surface of the main mold, and a liquid dielectric of an age hardening type is cast onto the conductor layer, and hardened. In a third step, the peripheral surface mold is detached from the main mold, and an unnecessary portion of the hardened dielectric is cut to thereby form a dielectric layer. In a fourth step, another conductor layer is formed on the dielectric layer. A method comprising these steps enables a dielectric board with a voluntary three-dimensionally curved surface to be manufactured with high accuracy.
REFERENCES:
patent: 3007997 (1961-11-01), Panariti
patent: 3536800 (1970-10-01), Hubbard
patent: 3889363 (1975-06-01), Davis
patent: 4200975 (1980-05-01), Debiec et al.
patent: 4772496 (1988-09-01), Maeda et al.
patent: 4828877 (1989-05-01), Kidd
patent: 4861640 (1989-08-01), Gurol
patent: 4937935 (1990-07-01), Calriou
Kabushiki Kaisha Toshiba
Talbot Brian K.
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