Method and apparatus for manufacturing a transistor-outline...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S125000

Reexamination Certificate

active

10732949

ABSTRACT:
A method of manufacturing an optoelectronic packaging comprises placing a solder preform between a metal cover and an insulating base, applying pressure to the metal cover and the insulating base, and applying a current through multiple conductive vias to heat the solder preform to melt.

REFERENCES:
patent: 4142286 (1979-03-01), Knuth et al.
patent: 5758816 (1998-06-01), Rabinovich
patent: 5982038 (1999-11-01), Toy et al.
patent: 6040624 (2000-03-01), Chambers et al.
patent: 6597944 (2003-07-01), Hadas
patent: 6709898 (2004-03-01), Ma et al.
patent: 6818464 (2004-11-01), Heschel
patent: 2004/0114882 (2004-06-01), Marquez et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method and apparatus for manufacturing a transistor-outline... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for manufacturing a transistor-outline..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for manufacturing a transistor-outline... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3784660

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.