Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-12-04
2001-09-04
Banks, Derris H. (Department: 3723)
Abrading
Abrading process
Glass or stone abrading
C451S063000, C451S036000
Reexamination Certificate
active
06283835
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and an apparatus for manufacturing a semiconductor integrated circuit, and more particularly, to a technique for reducing occurrence of wiring defects in the semiconductor integrated circuit during the process of forming a wiring structure, so as to elevate the quality level of the wiring structure and consequently the quality level of the semiconductor integrated circuit, thus to elevate the productivity of the semiconductor integrated circuit.
DESCRIPTION OF THE PRIOR ART
In a semiconductor integrated circuit, generally, semiconductor elements such as transistors etc. are formed on a semiconductor substrate, and also a wiring structure which connects the semiconductor elements one another or connects the semiconductor elements to external circuits is formed on the semiconductor substrate.
Conventionally, as the wiring structure as mentioned above, there has been used widely a wiring structure in which wiring patterns comprised of a polycrystalline silicon film, a high melting metal film, a high melting metal silicide film, a high melting metal polycide film, an aluminum film or an aluminum alloy film are combined. Recently among those, a high melting metal wiring, in which a tungsten wiring (W wiring) is typical one, has been used widely, since it has low resistance as compared with a polycrystalline silicon wiring pattern or a high melting metal polycide wiring pattern, also has generally good ability for step-coverage of the high melting metal film during a deposition process by means of the chemical vapor deposition method (the CVD method), and further has good reliability such as durability of electro-migration as compared with an aluminum wiring.
Further, as a fine contact member which connects the wiring pattern to the semiconductor substrate or to another lower wiring pattern, there has been used widely such a plug contact that is formed by filling a contact hole linked to the semiconductor substrate or to the lower wiring pattern, with a high melting metal film formed by the above-mentioned CVD method having good ability for step-coverage, for the purpose of reducing the contact resistance of the contact member, or elevating the reliability of the contact member. So there has been used widely a wiring structure which is entirely comprised of combination of the plug contacts and the wiring patterns.
On the other hand it is indispensable to elevate wiring density of the semiconductor integrated circuit for the purpose of achieving high integration and high functionality of the semiconductor integrated circuit. Therefore it is required to reduce the wiring pitch as possible as it can. Thus, as one of methods to be able to elevate the substantial wiring density extremely, a multi-layer type wiring structure also has been used.
Moreover the conventional wiring structures as mentioned above have been disclosed, for instance, in the documents of “A Double Level Metallization System Having 2 &mgr;m Pitch for Both Level”, T.Doan et. al., pp.13-20, VMIC Conference, 1988, and “SUBMICRON WIRING TECHNOLOGY WITH TUNGSTEN AND PLANARIZATION”, C. Kaanta et. al., pp.21-28, VMIC Conference, 1988.
However according to the conventional manufacturing methods of the wiring structure, there have been such problems that debris or residues formed in the wiring forming process often cause wiring defects, so that the quality level of the wiring structure and consequently the quality of the semiconductor integrated circuit are reduced, or the yield of wiring materials is reduced
Moreover in view of the present or future tendency as mentioned above that the wiring pitch is reducing more and more, and further the multi-layer wiring structure is used essentially, it is probable that the above-mentioned problems become more important.
Hereinafter a conventional manufacturing technique of a semiconductor integrated circuit and problems of the technique will be described concretely with reference to the accompanying drawings.
FIG. 16
is a vertical sectional view that shows an example of a conventional wiring structure of a semiconductor integrated circuit. In
FIG. 16
, there is shown a four-layer type wiring structure, in which a first stratiform wiring
305
(a gate electrode
303
) is comprised of a high melting metal polycide wiring, a second stratiform wiring
4
is comprised of a high melting metal wiring, a third stratiform wiring
7
and a fourth stratiform wiring
10
are respectively comprised of an aluminum wiring.
As shown in
FIG. 16
, in the conventional semiconductor integrated circuit, a semiconductor element
2
(transistor
2
) is formed on a silicon substrate
1
(silicon semiconductor substrate). Hereupon the tungsten polycide layer (W polycide layer, WSi
2
/poly-Si) which constructs the gate electrode
303
of the semiconductor element
2
is a part of the first stratiform wiring
305
.
A lower insulating film
3
comprised of SiO
2
or BPSG (Boro-Phosphorous Silicate Glass) etc. is formed by deposition process on the semiconductor element
2
(transistor
2
), and further on the lower insulating film
3
, there is formed contact holes
306
,
307
which are used for performing electrical connection between impurity diffusion layers
304
formed on the silicon substrate
1
or the first stratiform wiring
305
and other wirings.
Further the second stratiform wiring
4
(tungsten wiring) comprised of tungsten is provided on the lower insulating film
3
. The tungsten film
4
(W film) is generally formed by deposition process by means of the CVD method, and also has good ability of step-coverage, so that the contact holes
306
,
307
are filled with parts of the tungsten film
4
, as apparent from FIG.
16
.
Further a planed first interlayer insulating film
5
is formed on the second stratiform wiring
4
(tungsten wiring), and then there is formed in the first interlayer insulating film
5
a plurality of primary via-holes
313
for performing electrical connections between the second stratiform wiring
4
and other wirings. Moreover, as apparent from
FIG. 16
, the primary via-holes
313
are filled with parts of tungsten film, so that the parts of tungsten film form plug contacts
6
.
Moreover the third stratiform wiring
7
(aluminum wiring) is formed on the film
5
. Similarly, on the third stratiform wiring
7
(aluminum wiring), there are formed a second interlayer insulating film
8
, a plurality of secondary via-holes
321
in which plug contacts
9
comprised of tungsten for connecting electrically the third stratiform wiring
7
to other wirings are formed, the fourth stratiform wiring
10
(aluminum wiring) comprised of aluminum, and a protection insulating film
11
which covers the fourth stratiform film
10
.
Hereinafter a conventional manufacturing method of the wiring structure of the semiconductor integrated circuit will be described step by step with reference to
FIGS. 17-28
.
At first, as shown in
FIG. 17
, the semiconductor element
2
(transistor
2
) is formed on the surface of a silicon substrate
1
. The semiconductor element
2
(transistor
2
) is comprised of an element separating oxide film
301
, a gate oxide film
302
, the gate electrode
303
having a tungsten polycide structure (W polycide structure) comprised of a polycrystalline silicon
303
a
and a tungsten silicide
303
b
(WSiO
2
), and the impurity diffusion layers
304
.
Further the tungsten polycide layer (WSiO
2
/poly-Si) which constructs the gate electrode
303
is also formed on the element separating oxide film
301
, and then the layer is used as the first stratiform wiring
305
(
305
a
,
305
b
). And on the semiconductor element
2
(transistor
2
) and the first stratiform wiring
305
, there are formed by deposition process the lower insulating film
3
comprised of silicon oxide film (SiO
2
), BPSG (Boro-Phosphorous Silicate Glass) film which is a doped silicon oxide film containing boron (B) or phosphorous (P), and so on.
Next, as shown in
FIG. 18
, the contact holes
306
,
307
are formed at a predetermined p
Fujiki Noriaki
Harada Shigeru
Tanaka Tsutomu
Yamashita Takashi
Banks Derris H.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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