Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
1996-07-26
2001-08-21
Nguyen, Chau (Department: 2663)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S412000, C711S147000
Reexamination Certificate
active
06278711
ABSTRACT:
This application is related to contemporaneously filed U.S. patent application Ser. No. 08/381,110 titled “METHOD AND APPARATUS FOR SWITCHING, MULTICASTING, MULTIPLEXING AND DEMULTIPLEXING AN ATM CELL” filed on Jan. 31, 1995 by Mahesh N. Ganmukhi and Brian L. Jordan, now U.S. Pat. No. 5,541,918 issued Jul. 30, 1996 having attorney docket number FORE-10.
FIELD OF THE INVENTION
The present invention relates to a memory device and particularly to a semiconductor memory device having on the same integrated circuit device a mechanism for reading and writing an entire ATM cell into the memory array in one read or write cycle. The present invention relates also to the semiconductor memory device having multiple ports, i.e., multiple input and output paths, geared towards ATM cell input and output. The present invention relates also to an ATM switch, an ATM cell rate multiplexer and ATM cell rate demultiplexer.
BACKGROUND OF THE INVENTION
The unit of transmission used in the ATM is a cell. An ATM cell contains 53 bytes or 424 bits of information. These cells are transferred at one of the standard transmission rates, e.g., these cells may be transferred at OC-
1
(51.84 megabits/second) or OC-
3
(155.52 megabits/second) or OC-
12
(622.08 megabits/second) or OC-
24
(1.244 gigabits/second) or OC-
48
(2.488 gigabits/second) and so on. A very high storage capacity and high transfer (input and output) speed storage devices are very much desirable in the ATM network components. The DRAM, Dynamic Random Access Memory, provide lower cost per bit storage capability and provide more memory in the same unit of area compared to most other semiconductor memory devices. For this reason, DRAMs are excellent choice where large quantities of data need to be stored.
There are number of disadvantages of using a DRAM in a conventional way to store ATM cells. One can use the commercially available DRAMs to store the ATM cells but the these DRAMs offer a small number of data input/output pins, e.g., 1, 4, 8, 16 or 18 bits. Therefore, if one desires to construct a cell storage device capable of transferring an entire ATM cell at a time, one has to use many such DRAM chips. For example, using an 8 data bit wide DRAM one has to use at least 53 DRAM chips in parallel.
The speeds at which DRAMs operate, i.e., read/write the external data, are relatively slow. For example, some of the commercially available DRAM chips have memory cycle times of 90, 100, 120, 130 nanoseconds, etc. If one decides to use one such DRAM to store (write) or read an ATM cell, 8 bits at a time, then it would take at least 53 write cycles to store or read the entire cell.
Presently, DRAM memory devices are not commercially available that can read or write an entire ATM cell, in a row of memory array from the external world, in one memory cycle.
The present invention provides a capability of reading or writing an entire ATM cell into a DRAM in one memory cycle and therefore provides a solution for high capacity cell storage and high speed ATM cell input and output with the ATM network external to the integrated circuit device.
SUMMARY OF THE INVENTION
The present invention pertains to an apparatus for manipulating, such as buffering and switching, ATM cells, preferably on an integrated circuit device. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the ATM cell from or into the memory array. Preferably, the ATM cell is read or written from external to the integrated circuit device, into the memory array.
The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network.
The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I≧1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O≧1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle.
The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.
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patent: 5241536 (1993-08-01), Grimble et al.
patent: 5309395 (1994-05-01), Dickinson et al.
patent: 5309432 (1994-05-01), Kanakia
patent: 5517495 (1996-05-01), Lund et al.
patent: 5568651 (1996-10-01), Medina et al.
patent: 5602853 (1997-02-01), Ben-Michael
patent: 5619500 (1997-04-01), Hiekali
patent: 5758085 (1998-05-01), Kouoheris et al.
Micron Semiccononductor, Inc., DRAM 1993 Data Book, pp. 1-14 to 1-19, Mar. 1993.*
Micron Semiccononductor, Inc., DRAM 1993 Data Book, pp. 3-223-3-243, Mar. 1993.
Ganmukhi Mahesh N.
Jordan Brian L.
Hyun Soon-Dong
Marconi Communications Inc.
Nguyen Chau
Schwartz Ansel M.
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