Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent
1997-10-10
2000-12-26
Donaghue, Larry D.
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
712 13, 712 12, G06F 1500
Patent
active
061675024
ABSTRACT:
A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
REFERENCES:
patent: 5065339 (1991-11-01), Vassiliadis et al.
patent: 5146420 (1992-09-01), Vassiliadis et al.
patent: 5146543 (1992-09-01), Vassiliadis et al.
patent: 5148515 (1992-09-01), Vassiliadis et al.
patent: 5475856 (1995-12-01), Kogge
patent: 5542026 (1996-07-01), Pechanek et al.
patent: 5546336 (1996-08-01), Pechanek et al.
patent: 5566342 (1996-10-01), Denneau et al.
patent: 5577262 (1996-11-01), Pechanek et al.
patent: 5612908 (1997-03-01), Pechanek et al.
patent: 5682491 (1997-10-01), Pechanek et al.
Pechanek et al. "Multiple-Fold Clustered Processor Mesh Array", Proceedings Fifth NASA Symposium on VLSI Design, pp. 8.4.1-11, Nov. 4-5-1993, University of New Mexico, Albuquerque, New Mexico.
Pechanek et al. "A Massively Parallel Diagonal Fold Array Processor", 1993 International Conference on Application Specific Array Processors, pp. 140-143, Oct. 25-27, 1993, Venice, Italy.
L. Uhr, Multi-Computer Architectures for Artificial Intelligence, New York, N.Y., John Wiley & Sons, Ch. 8, p. 97, 1987.
R. Cypher and J.L.C. Sanz, "SIMD Architectures and Alogorithms for Image Processing and Computer Vision", IEEE Transactions on Acoustics, Speech and Signal Processing, vol. 37, No. 12, pp. 2158-2174, Dec. 1989.
K.E. Batcher, "Design of a Massively Parallel Processor", IEEE Transactions on Computers, vol. C-29, No. 9, pp. 836-840, Sep. 1980.
Robert Cypher and Jorge L.C. Sanz, "The SIMD Model of Parallel Computation" 1994 Springer-Verlag, New York, pp. 61-68.
F. Thomas Leighton, "Introduction To Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes," 1992 Morgan Kaufman Publishers, Inc., San Mateo, CA, pp. 389-404.
J. Granata, M. Conner, R. Tolimieri, "The Tensor Product: A Mathematical Programming Language for FFTs and Other Fast DSP Operations", IEEE Sp magazine, pp. 40-48, Jan. 1992.
J.R. Johnson, R.W. Johnson, D. Rodriguez, and R. Tolimieri, "A Methodology for Designing, Modifying, and Implementing Fourier Transform Algorithms on Various Architectures", Circuits Systems Signal Process, vol. 9, No. 4.
Barry Edwin F.
Drabenstott Thomas L.
Pechanek Gerald G.
Pitsianis Nikos P.
Billions of Operations Per Second, Inc.
Donaghue Larry D.
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