Method and apparatus for managing timing requirement specificati

Details Method and apparatus for managing timing requirement specificati Method and apparatus for managing timing requirement specificati

1996-02-23

1996-12-03

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, 395601, G06F 1750

Patent

active

055814735

ABSTRACT:
A repository, a loader, a model generator, a constraint generator, and a number of timing analysis tools, are provided for managing timing requirement specifications and measurements, and generating timing models and constraints of a VLSI circuit. The repository stores the timing specifications and measurements for each pin instances and each flow through arc instances. Timing specifications and measurements are identified by their classes including at least one current specification class and at least one measurement class for one timing analysis tool. Additionally, the repository stores a number of characteristics for each pin instance, the pin compositions of each net, and the hierarchical relationship of the functional block instances. The loader loads the various information into the repository. The timing model generator generates the timing models for the various functional blocks, using the stored information in the repository. The timing constraint generator in cooperation with the timing model generator and at least one timing analysis tool generates the timing constraints for the various functional block instances, using the stored information in the repository, the generated timing models of the functional blocks, and a number of timing analysis scripts.

REFERENCES:
patent: 4517661 (1985-05-01), Graf et al.
patent: 4827427 (1989-05-01), Hyduke
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5019961 (1991-05-01), Addesso et al.
patent: 5050091 (1991-09-01), Rubin
patent: 5084824 (1992-01-01), Lam et al.
patent: 5089985 (1992-02-01), Chang et al.
patent: 5095454 (1992-03-01), Huang
patent: 5140526 (1992-08-01), McDermith et al.
patent: 5150308 (1992-09-01), Hooper et al.
patent: 5164908 (1992-11-01), Igarashi
patent: 5210700 (1993-05-01), Tom
patent: 5220512 (1993-06-01), Watkins et al.
patent: 5222030 (1993-06-01), Dangeld et al.
patent: 5239481 (1993-08-01), Brooks et al.
patent: 5272651 (1993-12-01), Bush et al.
patent: 5278769 (1994-01-01), Bair et al.
patent: 5333032 (1994-07-01), Matsumoto et al.
Arya et al, "Automatic Generation of Digital System Schematic Diagrams," 22nd design Automation Conference, 1985, Paper 24.4, pp. 388-395.
Afsarmanesh et al., "The EVE VLSI Information Management Environment," 1989 Int'l Computer-Aided design Conference, pp. 384-387.
Chen et al., "An Intelligent Component Database for Behavioral Synthesis," 1990 27th ACM/IEEE Design Automation Conference, Paper 8.4, pp. 150-155.
Mueller-Glaser et al., "An Approach to Computer-Aided Specification, "IEEE Journal of Solid-State Circuits, vol. 25, No 2, Apr. 1990, pp. 335-345.
Toyoda et al., "A Fully Integrated Characterization ? Management System for ASIC Libraries,"1992 ASIC Conference and Exhibit, pp. 245-248.

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