Patent
1994-11-17
1996-12-03
Ray, Gopal C.
395282, 39518301, G06F 1300, H01R 909, H01R 13642, H05K 710
Patent
active
055817122
ABSTRACT:
Circuitry and logic are provided to a bus control module of a system bus of a computer system to inject the bus control module into, and win a system test master arbitration process initiated by a live inserted and successfully self tested CPU or I/O board. However, upon winning the system test master arbitration, the bus control module will inform the live inserted CPU or I/O board that it is not interested in having the CPU or I/O board in participating in system wide testing. In fact, the bus control module will not even initiate any system wide testing. As a result, CPU or I/O boards equipped with circuitry and logic to support certain required power on/reset testing protocol may be live inserted into the system without modifications, and without interruption to system operation.
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Finger, Roger, Multibus II Live Insertion of Boards Draft PSB Addendum, Sep. 5, 1991, Multibus Manufacturers Group.
Intel Corporation
Ray Gopal C.
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