Method and apparatus for managing failure of a system clock in a

Details Method and apparatus for managing failure of a system clock in a Method and apparatus for managing failure of a system clock in a

1997-08-18

1999-05-11

Heckler, Thomas M.

39518401, G06F1/04

Patent

active

059037482

ABSTRACT:
Under software control, a loss of clock detect circuit (24) can be enabled to detect loss of clock. A plurality of different clock signals, including the input reference clock (34) to the PLL (12) and the feedback (36) from the PLL (12), are monitored by the loss of clock circuit (24). When the currently selected system clock (38) signal is lost, a control circuit (28) can select an optimal back-up clocking mode based on which clock signals were lost. One such selectable mode is to utilize the input reference clock (34) directly instead of the PLL (12). Another such selectable mode is to utilize the PLL (12) in a self-clocked mode to provide the system clock (38).

REFERENCES:
patent: 4651277 (1987-03-01), Sakaji
patent: 4691126 (1987-09-01), Splett et al.
patent: 4931748 (1990-06-01), McDermott et al.
patent: 4982116 (1991-01-01), Lee
patent: 5161175 (1992-11-01), Parker et al.
patent: 5561390 (1996-10-01), Hiiragizawa

Affiliated with

Also associated with

Rating

Method and apparatus for managing failure of a system clock in a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for managing failure of a system clock in a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for managing failure of a system clock in a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-253797