Method and apparatus for managing concurrent access to multiple

Details Method and apparatus for managing concurrent access to multiple Method and apparatus for managing concurrent access to multiple

1994-09-27

1996-04-23

Zimmerman, Mark K.

395163, G06T 1540

Patent

active

055111548

ABSTRACT:
A memory apparatus includes a circuit for receiving and serially storing a plurality of instructions and a plurality of buffer memories each including a buffer controller for regulating access to that buffer. Also included is a circuit, connected to each buffer controller and the receiving circuit, for accessing one or more of said buffers in response to a first serially stored instruction while, in response to at least one other serially stored instruction, concurrently accessing at least one remaining buffer.

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