Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Patent
1994-01-11
1996-10-22
Gorgos, Kathryn
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
205128, C25D 502
Patent
active
055672957
ABSTRACT:
An inexpensive method for fabricating a staggered edge connector for a circuit board. The method is cost effective and includes numerous advantages over the prior art, including allowing more area for signal routing and removing the problems associated with capacitive stubs on edge connector traces associated with prior art designs. The method begins with creating a staggered plurality of blades or fingers. A plating bus is formed on these staggered blades by connecting a gold plating bus to one of the contact pads and then shorting together or connecting the signal lines via a shorting bus. The shorting bus is placed flush with the innermost edge of the edge connector well outside of the actual wipe area of the connectors. The board then undergoes a standard semi-additive process, as well as a final etch and subsequent gold plating. The shorting bar is then drilled out. Due to the placement of the shorting bar flush with the innermost edge of the edge connectors, the resultant vias do not occupy valuable signal routing area. Further, the drilling operation does not produce any capacitive stubs, thereby alleviating any cosmetic or performance problems associated with capacitive stubs, while not adding any additional time or cost to the board.
REFERENCES:
patent: 3825999 (1974-07-01), Rubey
patent: 4000045 (1976-12-01), Rotzow
Pecone Victor K.
Swamy Deepak N.
Dell USA L.P.
Gorgos Kathryn
Leader William T.
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