Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2011-07-26
2011-07-26
Huynh, Andy (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C257S712000, C257S734000, C257S778000
Reexamination Certificate
active
07985621
ABSTRACT:
A method of packaging a plurality of semiconductor chips comprises: providing a substrate panel having a first coefficient of thermal expansion (CTE); providing a carrier having a second CTE that is less than the first CTE; heating the substrate panel and the carrier to first and second elevated temperatures respectively; mounting the substrate panel at about the first elevated temperature to the carrier, the carrier being at said second elevated temperature, to provide a connection between the carrier and the substrate panel; and cooling the carrier and the substrate panel from the first and second elevated temperatures thereby putting the substrate panel into tension in at least one direction. A stiffener panel may be affixed to the substrate panel and heated to an elevated temperature and while the substrate panel is heated to an elevated temperature. A plurality of dies may be mounted and electrically connected to the substrate panel. Under-filling of the plurality of dies may occur with the stiffener panel affixed to the substrate panel.
REFERENCES:
patent: 4812191 (1989-03-01), Ho et al.
patent: 5866852 (1999-02-01), Benz et al.
patent: 5949137 (1999-09-01), Domadia et al.
patent: 6124637 (2000-09-01), Freyman et al.
patent: 6191360 (2001-02-01), Tao et al.
patent: 6284569 (2001-09-01), Sheppard et al.
patent: 6338985 (2002-01-01), Greenwood
patent: 6342434 (2002-01-01), Miyamoto et al.
patent: 6576073 (2003-06-01), Hilton et al.
patent: 6780733 (2004-08-01), Chason et al.
patent: 6903278 (2005-06-01), Sathe
patent: 6924168 (2005-08-01), Tuttle
patent: 6949404 (2005-09-01), Fritz et al.
patent: 6956291 (2005-10-01), Li
patent: 7045890 (2006-05-01), Xie et al.
patent: 2001/0052647 (2001-12-01), Plepys et al.
patent: 2003/0000736 (2003-01-01), Sathe
patent: 2003/0045028 (2003-03-01), Tsao et al.
patent: 2003/0157810 (2003-08-01), Honda
patent: 2005/0001311 (2005-01-01), Ho et al.
patent: 2005/0056942 (2005-03-01), Pogge et al.
patent: 2006/0226538 (2006-10-01), Kawata
patent: 2007/0096305 (2007-05-01), Fuergut et al.
patent: 1775768 (2007-04-01), None
patent: 2005302922 (2005-10-01), None
patent: WO/2005/086224 (2005-02-01), None
patent: WO 2005/119776 (2005-12-01), None
International Search Report dated Jan. 31, 2008 for PCT Application No. PCT/US2007/077115 pp. 1-14.
IBM Corporation; Anti-Curl Backer Sheet for ACT IV Stiffener; IBM Technical Disclosure; vol. 34, No. 6; Nov. 1, 1991; pp. 340-341.
Chan Vincent K.
McLellan Neil
Topacio Roden
ATI Technologies ULC
Brown Valerie
Huynh Andy
Vedder Price P.C.
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