Boots – shoes – and leggings
Patent
1994-10-14
1997-06-10
Teska, Kevin J.
Boots, shoes, and leggings
364488, 364489, 364491, 371 1, G06F 1900
Patent
active
056382910
ABSTRACT:
The present invention discloses a method and an apparatus for making digital integrated circuits by considering ramp delay and clock skew as constraints while minimizing the number of inserted buffers and overall wire length connecting components for large clock trees. The invention includes developing a set of circuit specifications including maximum clock skew, minimum driveability, and maximum ramp delay. These specifications are described in a hardware description language on a digital computer system, and a netlist is synthesized from this hardware description. A modified netlist is then formed by analyzing the netlist and inserting buffers into it to satisfy the circuit specifications of skew, driveabilility, and ramp delay. Thereafter, a digital integrated circuit is produced as specified by the modified netlist.
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Ashtaputre Sunil V.
Greidinger Jacob
Hartoog Mark R.
Hossain Moazzem M.
Hui Siu-Tong
Nguyen Tan Q.
Teska Kevin J.
VLSI Technology Inc.
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