Method and apparatus for making coplanar isolated regions of...

Details Method and apparatus for making coplanar isolated regions of... Method and apparatus for making coplanar isolated regions of...

2011-05-24

2011-05-24

Smith, Matthew S (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having air-gap dielectric

C257S276000, C257S522000, C257SE21564, C257SE21573, C257SE23013, C438S319000, C438S411000, C438S421000, C438S619000

Reexamination Certificate

active

07947566

ABSTRACT:
A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers.

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patent: 2002/0045325 (2002-04-01), Kuhn et al.
patent: 2002/0126725 (2002-09-01), Tayebati

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